LTC4372IDD-TRPBF Просмотр технического описания (PDF) - Analog Devices

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LTC4372IDD-TRPBF

Low Quiescent Current Ideal Diode Controller

Analog Devices 

LTC4372/LTC4373

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. IN = SOURCE =12V, SHDN = 0V, UV = 2V unless otherwise noted.

SYMBOL PARAMETER

CONDITIONS

MIN TYP MAX UNITS

IGATE(DOWN) GATE Pull-Down Current

Shutdown: SHDN = 2V, UV = 0V, ∆VGATE = 5V l 0.5

1

3

mA

Reverse Current: ∆VSD = –0.1V, ∆VGATE = 5V

l 70

130 230

mA

Reverse Battery: IN = SOURCE = –7V, GATE = –3V l 70

130 230

mA

VGATE(NEG) GND-GATE clamp

IGATE = 10mA (Note 3)

l –28 –32 –35

V

VSOURCE(TH) Reverse SOURCE Threshold for GATE Off GATE = 0V (Note 5)

l –0.9 –1.8 –2.7

V

tOFF

Gate Turn-Off Delay Time

ΔVSD = Step 0.1V to –0.8V, CGATE = 0pF, ΔVGATE <1V l

0.5

1.5

µs

tON

Gate Turn-On Delay Time

IN = 12V, SOURCE = OUT = 0V, ΔVGATE > 4.5V, l 100 500 1200

µs

CGATE = 0pF, SHDN = 2V to 0V, UV = 0V to 1.25V

LTC4372

I2UPU

2UPU Pull-Up Current

VSHDN

SHDN Threshold

VSHDN(HYST) SHDN Threshold Hysteresis

ISHDN

SHDN Leakage Current

LTC4373

SHDN Falling

SHDN = 1.2V

l –1

–2

–3

µA

l1

1.2

1.4

V

l2

15

40

mV

l

±1

±50

nA

VUV

VUV(HYST)

IUV(LK)

IUVOUT(LK)

UV Threshold

UV Threshold Hysteresis

UV Leakage Current

UVOUT Leakage Current

UV Falling

UV = 1.2V

UV = 2V, UVOUT = 1.2V

(C-Grade, I-Grade)

(H-Grade)

l 1.174 1.191 1.208

V

l2

15

40

mV

l

±1

±50

nA

l

±1

±50

nA

l

±1 ±200

nA

RUVOUT#

tUV

UVOUT Output Low Resistance

I = 2mA

Under Voltage Detect to UVOUT Assert Low UV = Step 1.25V to 1.1V

l

140 500

Ω

l 10

50

300

µs

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into device pins are positive; all currents out of

device pins are negative. All voltages are referenced to GND unless

otherwise specified.

Note 3: An internal clamp limits the GATE pin to a minimum of 10V above

SOURCE or 100V above GND. A second internal clamp limits the GATE pin

to a minimum of 28V below GND. Driving this pin to voltages beyond the

clamp may damage the device.

Note 4: When testing the single MOSFET configuration, IN is connected to

SOURCE. When testing the back-to-back MOSFET configuration, SOURCE

is left unconnected.

Note 5: SOURCE ≤ –1.8V triggers a 130mA pull-down current from GATE

to SOURCE. An internal clamp limits the GATE pin to a minimum of 28V

below GND. Driving SOURCE to voltages beyond the clamp may damage

the device.

Rev. 0

4

For more information www.analog.com

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