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M48T86MH1

5.0V PC Real-Time Clock

Unspecified 

M48T86

E (Chip Enable Input). The Chip Enable pin

must be asserted low for a bus cycle in the

M48T86 to be accessed. Bus cycles which take

place without asserting E will latch the addresses

present, but no data access will occur.

IRQ (Interrupt Request Output). The IRQ pin is

an open drain output that can be used as an inter-

rupt input to a processor. The IRQ output remains

low as long as the status bit causing the interrupt

is present and the corresponding interrupt-enable

bit is set. IRQ returns to a high impedance state

whenever Register C is read. The RST pin can

also be used to clear pending interrupts. The IRQ

bus is an open drain output so it requires an exter-

nal pull-up resistor to VCC.

RST (Reset Input). The M48T86 is reset when

the RST input is pulled low. With a valid VCC ap-

plied and a low on RST, the following events oc-

cur:

1. Periodic Interrupt Enable (PIE) Bit is cleared to

a zero (Register B; Bit 6);

2. Alarm Interrupt Enable (AIE) Bit is cleared to a

zero (Register B; Bit 5);

3. Update Ended Interrupt Request (UF) Bit is

cleared to a zero (Register C; Bit 4);

4. Interrupt Request (IRQF) Bit is cleared to a

zero (Register C Bit 7);

5. Periodic Interrupt Flag (PF) Bit is cleared to a

zero (Register C; Bit 6);

6. The device is not accessible until RST is re-

turned high;

7. Alarm Interrupt Flag (AF) Bit is cleared to a

zero (Register C; Bit 5);

8. The IRQ pin is in the high impedance state

9. Square Wave Output Enable (SQWE) Bit is

cleared to zero (Register B; Bit 3); and

10. Update Ended Interrupt Enable (UIE) is

cleared to a zero (Register B; Bit 4).

RCL (RAM Clear). The RCL pin is used to clear

all 114 storage bytes, excluding clock and control

registers, of the array to FF(hex) value. The array

will be cleared when the RCL pin is held low for at

least 100ms with the oscillator running. Usage of

this pin does not affect battery load. This function

is applicable only when VCC is applied.

R/W (READ/WRITE Input). The R/W pin is used

to latch data into the M48T86 and provides func-

tionality similar to W in other memory systems.

Non-Volatile RAM

The 114 general-purpose non-volatile RAM bytes

are not dedicated to any special function within the

M48T86. They can be used by the processor pro-

gram as non-volatile memory and are fully acces-

sible during the update cycle.

Figure 7. Intel Bus READ AC Waveform

AS

DS

R/W

tDAS

E

AD0-AD7

tCYC

tASW

tASD

tDSL

tDSH

tCS

tOD

tAS

tAH

tCH

tDHR

AI01647

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