M48T86MH1 Просмотр технического описания (PDF) - Unspecified

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M48T86MH1

5.0V PC Real-Time Clock

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OPERATION

Automatic deselection of the device ensures the

data integrity is not compromised should VCC fall

below specified Power-fail Deselect Voltage

(VPFD) levels (see Figure 16., page 22). The auto-

matic deselection of the device remains in effect

upon power up for a period of 200ms (max) after

VCC rises above VPFD, provided that the Real

Time Clock is running and the count-down chain is

not reset. This allows sufficient time for VCC to sta-

bilize and gives the system clock a wake-up period

so that a valid system reset can be established.

The block diagram in Figure 6., page 6 shows the

pin connections and the major internal functions of

the M48T86.

Signal Description

VCC, VSS. DC power is provided to the device on

these pins.The M48T86 uses a 5V VCC.

SQW (Square Wave Output). During normal op-

eration (e.g., valid VCC), the SQW pin can output a

signal from one of 13 taps. The frequency of the

SQW pin can be changed by programming Regis-

ter A as shown in Table 4., page 14. The SQW sig-

nal can be turned on and off using the SQWE Bit

(Register B; Bit 3). The SQW signal is not avail-

able when VCC is less than VPFD.

AD0-AD7 (Multiplexed Bi-Directional Address/

Data Bus). The M48T86 provides a multiplexed

bus in which address and data information share

the same signal path. The bus cycle consists of

two stages; first the address is latched, followed by

the data. Address/Data multiplexing does not slow

M48T86

the access time of the M48T86, because the bus

change from address to data occurs during the in-

ternal RAM access time. Addresses must be valid

prior to the falling edge of AS (see Figure

7., page 8), at which time the M48T86 latches the

address present on AD0-AD7. Valid WRITE data

must be present and held stable during the latter

portion of the R/W pulse (see Figure 8., page 9). In

a READ cycle, the M48T86 outputs 8 bits of data

during the latter portion of the DS pulse. The

READ cycle is terminated and the bus returns to a

high impedance state upon a high transition on R/

W.

AS (Address Strobe Input). A positive going

pulse on the Address Strobe (AS) input serves to

demultiplex the bus. The falling edge of AS causes

the address present on AD0-AD7 to be latched

within the M48T86.

MOT (Mode Select). The MOT pin offers the flex-

ibility to choose between two bus types (see Fig-

ure 9., page 9). When connected to VCC, Motorola

bus timing is selected. When connected to VSS or

left disconnected, Intel bus timing is selected. The

pin has an internal pull-down resistance of approx-

imately 20KΩ.

DS (Data Strobe Input). The DS pin is also re-

ferred to as READ (RD). A falling edge transition

on the Data Strobe (DS) input enables the output

during a a READ cycle. This is very similar to an

Output Enable (G) signal on other memory devic-

es.

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