M28F010-90 Просмотр технического описания (PDF) - Intel

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M28F010-90

1024K (128K x 8) CMOS FLASH MEMORY

Intel 

M28F010

COMMAND DEFINITIONS

When low voltage is applied to the VPP pin the con-

tents of the command register default to 00H en-

abling read-only operations

Placing high voltage on the VPP pin enables read

write operations Device operations are selected by

writing specific data patterns into the command reg-

ister Table 3 defines these M28F010 register

commands

Table 3 Command Definitions

Command

Bus

Cycles

First Bus Cycle

Second Bus Cycle

Req’d Operation(1) Address(2) Data(3) Operation(1) Address(2) Data(3)

Read Memory

1

Write

X

00H

Read intelligent Identifier Codes(4) 2

Write

X

90H

Read

IA

ID

Set-up Erase Erase(5)

2

Write

X

20H

Write

X

20H

Erase Verify(5)

2

Write

EA

A0H

Read

X

EVD

Set-up Program Program(6)

2

Write

X

40H

Write

PA

PD

Program Verify(6)

2

Write

X

C0H

Read

X

PVD

Reset(7)

2

Write

X

FFH

Write

X

FFH

NOTES

1 Bus operations are defined in Table 2

2 IA e Identifier address 00H for manufacturer code 01H for device code

EA e Address of memory location to be read during erase verify

PA e Address of memory location to be programmed

Addresses are latched on the falling edge of the Write-Enable pulse

3 ID e Data read from location IA during device identification (Mfr e 89H Device e B4H)

EVD e Data read from location EA during erase verify

PD e Data to be programmed at location PA Data is latched on the rising edge of Write-Enable

PVD e Data read from location PA during program verify PA is latched on the Program command

4 Following the Read inteligent ID command two read operations access manufacturer and device codes

5 Figure 5 illustrates the Quick-Erase Algorithm

6 Figure 4 illustrates the Quick-Pulse Programming Algorithm

7 The second bus cycle must be followed by the desired command register write

6

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