M28F010-90 Просмотр технического описания (PDF) - Intel

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M28F010-90

1024K (128K x 8) CMOS FLASH MEMORY

Intel 

M28F010

Table 2 M28F010 Bus Operations

Operation

Pins VPP(1) A0

A9

CE OE WE DQ0 – DQ7

Read

VPPL A0 A9 VIL VIL VIH Data Out

Output Disable

VPPL X

X VIL VIH VIH Tri-State

READ-ONLY Standby

intelligent Identifier (Mfr)(2)

VPPL

VPPL

X

X VIH X X Tri-State

VIL VID(7) VIL VIL VIH Data e 89H

intelligent Identifier (Device)(2) VPPL VIH VID(7) VIL VIL VIH Data e B4H

Read

VPPH A0

A9

VIL VIL VIH Data Out(3)

READ WRITE Output Disable

Standby(4)

VPPH X

VPPH X

X VIL VIH VIH Tri-State

X VIH X X Tri-State

Write

VPPH A0

A9

VIL VIH VIL Data In(5)

NOTES

1 VPPL may be ground a no-connect with a resistor tied to ground or as defined in the Characteristics Section VPPH is the

programming voltage specified for the device Refer to DC Characteristics When VPP e VPPL memory contents can be

read but not written or erased

2 Manufacturer and device codes may also be accessed via a command register write sequence Refer to Table 3 All other

addresses low

3 Read operations with VPP e VPPH may access array data or the intelligent Identifier codes

4 With VPP at high voltage the standby current equals ICC a IPP (standby)

5 Refer to Table 3 for valid Data-In during a write operation

6 X can be VIL or VIH

7 VID is the intelligent Identifier high voltage Refer to DC Characteristics

Or the system designer may choose to ‘‘hardwire’’

VPP making the high voltage supply constantly

available In this instance all operations are per-

formed in conjunction with the command register

The M28F010 is designed to accommodate either

design practice and to encourage optimization of

the processor-memory interface

Integrated Stop Timer

Sucessive command write cycles define the dura-

tions of program and erase operations specifically

the program or erase time durations are normally

terminated by associated program or erase verify

commands An integrated stop timer provides simpli-

fied timing control over these operations thus elimi-

nating the need for maximum program erase timing

specifications Programming and erase pulse dura-

tions are minimums only When the stop timer termi-

nates a program or erase operation the device

enters an inactive state and remains inactive until

receiving the appropriate verify or reset command

Write Protection

The command register is only active when VPP is at

high voltage Depending upon the application the

system designer may choose to make the VPP pow-

er supply switchable available only when memory

updates are desired When VPP e VPPL the con-

tents of the register default to the read command

making the 28F010 a read-only memory In this

mode the memory contents cannot be altered

Or the system designer may choose to ‘‘hardwire’’

VPP making the high voltage supply constantly

available In this case all Command Register func-

tions are inhibited whenever VCC is below the write

lockout voltage VLKO (See Power Up Down Protec-

tion) The 28F010 is designed to accommodate ei-

ther design practice and to encourage optimization

of the processor-memory interface

BUS OPERATIONS

Read

The M28F010 has two control functions both of

which must be logically active to obtain data at the

outputs Chip-Enable (CE) is the power control and

should be used for device selection Output-Enable

(OE) is the output control and should be used

to gate data from the output pins independent of

device selection Figure 6 illustrates read timing

waveforms

4

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