QL5632-33B-PQ208C Просмотр технического описания (PDF) - QuickLogic Corporation

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QL5632-33B-PQ208C

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5632 Enhanced QuickPCI Device Data Sheet Rev. C

Architecture Overview

The QL6432 device in the QuickLogic QuickPCI ESP (Embedded Standard Product) family

provides a complete and customizable PCI interface solution combined with programmable logic.

This device eliminates any need for the designer to worry about PCI bus compliance, yet allows

for the maximum 32-bit PCI bus bandwidth (132 MBps).

The programmable logic portion of the device contains 772 QuickLogic Logic Cells and

18 QuickLogic Dual-Port RAM Blocks. These configurable RAM blocks can be configured in

many width/depth combinations. They can also be combined with logic cells to form FIFOs, or

be initialized via Serial EEPROM on power-up and used as ROMs.

The QL6432 device meets PCI 2.3 electrical and timing specifications and has been fully

hardware-tested. This device also supports the Win'98 and PC'98 standards. The QL6432 device

features 2.5 V operation with multi-volt compatible I/Os. The device can easily operate in 3 V

embedded systems and is fully compatible with 3.3 V applications.

PCI Controller

The PCI Controller is a 32-bit/33 MHz PCI 2.3 Compliant Master/Target Controller capable of

infinite length Master Write and Read transactions at zero wait states

(132 MBps).

The Master will never insert wait states during transfers, so data is supplied or received by FIFOs

that can be configured in the programmable region of the device. The Master is capable of

initiating any type of PCI commands, including configuration cycles and Memory Write and

Invalidate (MWI). This enables the QL6432 device to act as a PCI host. The Master Controller will

most often be operated by a DMA Controller in the programmable region of the device. DMA

Controller reference design is available and will be included in the QuickWorks 9.3 design

software.

The Target interface offers full PCI Configuration Space and flexible target addressing. It supports

zero-wait-state target Write and one-wait-state target Read operations. It also supports retry,

disconnect with/without data transfer, and target abort requested by the back end. Any number

of 32-bit BARs may be configured as either memory or I/O space. All required and optional PCI

2.3 Configuration Space registers can be implemented within the programmable region of the

device. A reference design of a Target Configuration and Addressing module is available and will

be included in the QuickWorks 9.3 design software.

The interface ports are divided into a set of ports for master transactions and a set for target

transactions. The Master DMA controller and Target Configuration Space and Address Decoding

are done in the programmable logic region of the device. These functions are not timing critical,

so leaving these elements in the programmable region allows the greatest degree of flexibility to

the designer. Reference DMA controller, Configuration Space, and Address Decoding blocks are

readily available so that the design cycle can be minimized.

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