IDT70V658S Просмотр технического описания (PDF) - Unspecified
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IDT70V658S Datasheet PDF : 23 Pages
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IDT70V658S
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Description
The IDT70V658 is a high-speed 64K x 36 Asynchronous Dual-Port
Static RAM. The IDT70V658 is designed to be used as a stand-alone
2304K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-
Port RAM for 72-bit-or-more word system. Using the IDT MASTER/
SLAVE Dual-Port RAM approach in 72-bit or wider memory system
applications results in full-speed, error-free operation without the need for
additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (either CE0 or CE1) permit
the on-chip circuitry of each port to enter a very low standby power mode.
The 70V658 can support an operating voltage of either 3.3V or 2.5V
on one or both ports, controlled by the OPT pins. The power supply for
the core of the device (VDD) remains at 3.3V.
Pin Configurations(1,2,3,4)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
A
I/O19L I/O18L VSS TDO
NC
NC
A12L
A8L BE1L
VDD SEML INTL
A4L
A0L
OPTL I/O17L VSS
A
B
I/O20R VSS I/O18R TDI
NC
A13L
A9L BE2L CE0L
VSS BUSYL A5L A1L
B VSS VDDQR I/O16L I/O15R
C
VDDQL I/O19R VDDQR VDD
NC A14L
A10L BE3L CE1L
VSS
R /WL A 6L
A2L
VDD I/O16R I/O15L VSS
C
D
I/O22L VSS I/O21L I/O20L A15L A11L
A7L
BE0L
VDD
OEL
NC
A3L
VDD
D I/O17R VDDQL I/O14L I/O14R
E
I/O23L I/O22R VDDQR I/O21R
E I/O12L I/O13R VSS I/O13L
F
VDDQL I/O23R I/O24L VSS
F VSS I/O12R I/O11L VDDQR
G
I/O26L VSS I/O25L I/O24R
H
VDD I/O26R VDDQR I/O25R
J
VDDQL VDD
VSS
VSS
K
I/O28R VSS I/O27R VSS
70V658BF
BF-208(5)
208-Ball fpBGA
Top View(6)
G I/O9L VDDQL I/O10L I/O11R
H VDD I/O9R VSS I/O10R
VSS
VDD
J VSS VDDQR
I/O7R VDDQL I/O8R VSS
K
L
I/O29R I/O28L VDDQR I/O27L
L I/O6R I/O7L VSS I/O8L
M
VDDQL I/O29L I/O30R VSS
VSS
M I/O6L I/O5R VDDQR
N
I/O31L VSS I/O31R I/O30L
N I/O3R VDDQL I/O4R I/O5L
P
I/O32R I/O32L VDDQR I/O35R TRST
NC
A 12R
A8R BE1R
VDD SEMR
INTR A4R
I/O2L I/O3L
VSS
P I/O4L
R
VSS I/O33L I/O34R TCK NC
A13R
A9R BE2R CE0R
VSS BUSYR A5R
A1R
R VSS VDDQL I/O1R VDDQR
T
I/O33R I/O34L VDDQL TMS NC
A14R A10R BE3R CE1R VSS R/WR A6R
A2R
VSS
I/O0R
T VSS I/O2R
U
VSS I/O35L VDD
NC A15R A11R
A7R BE0R
VDD
OER
M/S
A3R
U A0R VDD OPTR I/O0L I/O1L
5613 tbl 02b
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V)
3. All VSS pins must be connected to ground.
4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
2
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