IS61NP25632 Просмотр технического описания (PDF) - Integrated Silicon Solution
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IS61NP25632
Integrated Silicon Solution
IS61NP25632 Datasheet PDF : 20 Pages
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ISSI IS61NP25632 IS61NP25636 IS61NP51218
®
IS61NLP25632 IS61NLP25636 IS61NLP51218
256K x 32, 256K x 36 and 512K x 18
PIPELINE 'NO WAIT' STATE BUS SRAM
NOVEMBER 2002
FEATURES
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address,
data and control
• Interleaved or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining for TQFP
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP and 119 PBGA packages
• Single +3.3V power supply (± 5%)
• NP Version: 3.3V I/O Supply Voltage
• NLP Version: 2.5V I/O Supply Voltage
• Industrial temperature available
DESCRIPTION
The 8 Meg 'NP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
network and communications customers. They are
organized as 262,144 words by 32 bits, 262,144 words
by 36 bits and 524,288 words by 18 bits, fabricated with
ISSI's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when WE is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frequency
-133
4.2
7.5
133
-100
Units
5
ns
10
ns
100
MHz
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-47744
1
Rev. B
11/19/02
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