IS61LPS25632J Просмотр технического описания (PDF) - Integrated Silicon Solution
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IS61LPS25632J
Integrated Silicon Solution
IS61LPS25632J Datasheet PDF : 29 Pages
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IS61LPS25632T/D/J
IS61LPS25636T/D/J
IS61LPS51218T/DJ
ISSI ®
256K x 32, 256K x 36, 512K x 18
PRELIMINARY INFORMATION
SYNCHRONOUS PIPELINED,
APRIL 2002
SINGLE-CYCLE DESELECT STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Linear burst sequence control using MODE
input
• Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Power Supply
+3.3V Vcc
+3.3V or 2.5 VccQ (I/O)
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
• T Version (three chips selects)
• D Version (two chips selects)
• J Version (PBGA Package with JTAG)
FAST ACCESS TIME
Symbol
Parameter
tKQ Clock Access Time
tKC Cycle Time
Frequency
DESCRIPTION
The ISSI IS61LPS25632T/D/J, IS61LPS25636T/D/J, and
IS61LPS51218T/D/J are high-speed, low-power synchro-
nous static RAMs designed to provide burstable, high-
performance memory for communication and networking appli-
cations. The IS61LPS25632T/D/J is organized as 262,144
words by 32 bits and the IS61LPS25636T/D/J is organized
as 262,144 words by 36 bits. The IS61LPS51218T/D/J is
organized as 524,288 words by 18 bits. Fabricated with
ISSI's advanced CMOS technology, the device integrates
a 2-bit burst counter, high-speed SRAM core, and high-drive
capability outputs into a single monolithic circuit. All syn-
chronous inputs pass through registers controlled by a
positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be one to four
bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write enable
(BWE).input combined with one or more individual byte write
signals (BWx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address ad-
vance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Inter-
leave burst is achieved when this pin is tied HIGH or left
floating.
-250
2.6
4
250
-225
2.8
4.4
225
-200
3.1
5
200
-166
3.5
6
166
Units
ns
ns
MHz
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
PRELIMINARYINFORMATION Rev. 00B
04/29/02
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