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IDT82V2081PPG

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

IDT82V2081

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-1 Pin Description (Continued)

Name

RCLK

MCLK

LOS

REF

MODE1

MODE0

Type TQFP 44 QFN 48

Pin No. Pin No.

Description

O

4

4 RCLK: Receive Clock output

This pin outputs 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode receive clock. Under LOS condition with AIS

enabled (bit AISE=1), RCLK is derived from MCLK. In clock recovery mode, this signal provides the clock recovered from

the RTIP/RRING signal. The receive data (RD in single rail mode or RDP and RDN in dual rail mode) is clocked out of

the device on the active edge of RCLK. If clock recovery is bypassed, RCLK is the exclusive OR (XOR) output of the dual

rail slicer data RDP and RDN. This signal can be used in applications with external clock recovery circuitry.

I

9

9 MCLK: Master Clock input

A built-in clock system that accepts selectable 2.048MHz reference for E1 operating mode and 1.544MHz reference for

T1/J1 operating mode. This reference clock is used to generate several internal reference signals:

• Timing reference for the integrated clock recovery unit.

• Timing reference for the integrated digital jitter attenuator.

• Timing reference for microcontroller interface.

• Generation of RCLK signal during a loss of signal condition.

• Reference clock to transmit All Ones, all zeros, PRBS/QRSS pattern as well as activate or deactivate Inband

Loopback code if MCLK is selected as the reference clock. Note that for ATAO and AIS, MCLK is always used as

the reference clock.

• Reference clock during the Transmit All Ones (TAO) condition or sending PRBS/QRSS in hardware control mode.

The loss of MCLK will turn TTIP/TRING into high impedance status.

O

7

7 LOS: Loss of Signal Output

This is an active high signal used to indicate the loss of received signal. When LOS pin becomes high, it indicates the loss

of received signal. The LOS pin will become low automatically when valid received signal is detected again. The criteria

of loss of signal are described in 3.6 Los And AIS Detection.

I

43

46 REF: reference resister

An external resistor (3 K, 1%) is used to connect this pin to ground to provide a standard reference current for internal

circuit.

I

17

19 MODE[1:0]: operation mode of Control interface select

16

18 The level on this pin determines which control mode is used to control the device as follows:

RCLKE

I

MODE[1:0]

00

01

10

11

Control Interface mode

Hardware interface

Serial Microcontroller Interface

Parallel –Multiplexed -Motorola Interface

Parallel –Multiplexed -Intel Interface

• The serial microcontroller Interface consists of CS, SCLK, SCLKE, SDI, SDO and INT pins. SCLKE is used for the

selection of the active edge of SCLK.

• The parallel multiplexed microcontroller interface consists of CS, AD[7:0], DS/RD, R/W/WR, ALE/AS, ACK/RDY

and INT pins. (refer to 3.12 Microcontroller Interfaces for details)

• Hardware interface consists of PULS[3:0], THZ, RCLKE, LP[1:0], PATT[1:0], JA[1:0], MONT, TERM, EQ, RPD,

MODE[1:0] and RXTXM[1:0]

11

11 RCLKE: the active edge of RCLK select

In hardware control mode, this pin selects the active edge of RCLK

• L= select the rising edge as the active edge of RCLK

• H= select the falling edge as the active edge of RCLK

In software control mode, this pin should be connected to GNDIO.

Pin Description

11

January 7, 2019

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