IDT82P2282PF Просмотр технического описания (PDF) - Integrated Device Technology

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IDT82P2282PF

Dual T1/E1/J1 Long Haul / Short Haul Transceiver

Integrated Device Technology 

IDT82P2282

DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER

4 OPERATION ................................................................................................................................................................... 108

4.1 POWER-ON SEQUENCE ............................................................................................................................................................................ 108

4.2 RESET ......................................................................................................................................................................................................... 108

4.3 RECEIVE / TRANSMIT PATH POWER DOWN .......................................................................................................................................... 108

4.4 MICROPROCESSOR INTERFACE ............................................................................................................................................................ 109

4.4.1 SPI Mode ....................................................................................................................................................................................... 109

4.4.2 Parallel Microprocessor Interface .............................................................................................................................................. 110

4.5 INDIRECT REGISTER ACCESS SCHEME ................................................................................................................................................ 111

4.5.1 Indirect Register Read Access ................................................................................................................................................... 111

4.5.2 Indirect Register Write Access ................................................................................................................................................... 111

5 PROGRAMMING INFORMATION .................................................................................................................................. 112

5.1 REGISTER MAP .......................................................................................................................................................................................... 112

5.1.1 T1/J1 Mode .................................................................................................................................................................................... 112

5.1.1.1 Direct Register ................................................................................................................................................................ 112

5.1.1.2 Indirect Register ............................................................................................................................................................. 117

5.1.2 E1 Mode ........................................................................................................................................................................................ 118

5.1.2.1 Direct Register ................................................................................................................................................................ 118

5.1.2.2 Indirect Register ............................................................................................................................................................. 123

5.2 REGISTER DESCRIPTION ......................................................................................................................................................................... 125

5.2.1 T1/J1 Mode .................................................................................................................................................................................... 126

5.2.1.1 Direct Register ................................................................................................................................................................ 126

5.2.1.2 Indirect Register ............................................................................................................................................................. 227

5.2.2 E1 Mode ........................................................................................................................................................................................ 240

5.2.2.1 Direct Register ................................................................................................................................................................ 240

5.2.2.2 Indirect Register ............................................................................................................................................................. 342

6 IEEE STD 1149.1 JTAG TEST ACCESS PORT ............................................................................................................ 357

6.1 JTAG INSTRUCTIONS AND INSTRUCTION REGISTER (IR) ................................................................................................................... 358

6.2 JTAG DATA REGISTER ............................................................................................................................................................................. 359

6.2.1 Device Identification Register (IDR) ........................................................................................................................................... 359

6.2.2 Bypass Register (BYP) ................................................................................................................................................................ 359

6.2.3 Boundary Scan Register (BSR) ................................................................................................................................................... 359

6.3 TEST ACCESS PORT CONTROLLER ....................................................................................................................................................... 361

7 PHYSICAL AND ELECTRICAL SPECIFICATIONS ...................................................................................................... 364

7.1 ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 364

7.2 RECOMMENDED OPERATING CONDITIONS .......................................................................................................................................... 364

7.3 D.C. CHARACTERISTICS .......................................................................................................................................................................... 365

7.4 DIGITAL I/O TIMING CHARACTERISTICS ................................................................................................................................................ 366

7.4.1 In Non-Multiplexed Mode ............................................................................................................................................................. 366

7.4.2 In Multiplexed Mode ..................................................................................................................................................................... 367

7.5 CLOCK FREQUENCY REQUIREMENT ..................................................................................................................................................... 367

7.6 T1/J1 LINE RECEIVER ELECTRICAL CHARACTERISTICS .................................................................................................................... 368

7.7 E1 LINE RECEIVER ELECTRICAL CHARACTERISTICS ......................................................................................................................... 369

7.8 T1/J1 LINE TRANSMITTER ELECTRICAL CHARACTERISTICS ............................................................................................................. 370

7.9 E1 LINE TRANSMITTER ELECTRICAL CHARACTERISTICS ................................................................................................................. 371

7.10 JITTER TOLERANCE ................................................................................................................................................................................. 372

7.10.1 T1/J1 Mode .................................................................................................................................................................................... 372

7.10.2 E1 Mode ........................................................................................................................................................................................ 373

7.11 JITTER TRANSFER .................................................................................................................................................................................... 374

7.11.1 T1/J1 Mode .................................................................................................................................................................................... 374

7.11.2 E1 Mode ........................................................................................................................................................................................ 375

7.12 MICROPROCESSOR TIMING SPECIFICATION ........................................................................................................................................ 376

7.12.1 Motorola Non-Multiplexed Mode ................................................................................................................................................. 376

7.12.1.1 Read Cycle Specification ............................................................................................................................................... 376

Table of Contents

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August 20, 2009

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