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IDT82P2282PFG

Dual T1/E1/J1 Long Haul / Short Haul Transceiver

Integrated Device Technology 

IDT82P2282

DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER

Name

Type Pin No.

Description

RSFS[1] / MRSFS Output / Input 77 RSFS[1:2]: Receive Side System Frame Pulse for Link 1 ~ 2

RSFS[2]

69 In T1/J1 Receive Clock Master mode, RSFSn outputs the pulse to indicate each F-bit, every second F-bit in SF frame,

the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame or the first F-bit of every second SF multi-frame.

In T1/J1 Receive Clock Slave mode, RSFSn inputs the pulse at a rate of integer multiple of 125 µs to indicate the start

of a frame.

In E1 Receive Clock Master mode, RSFSn outputs the pulse to indicate the Basic frame, CRC Multi-frame, Signaling

Multi-frame, or both the CRC Multi-frame and Signaling Multi-frame, or the TS1 and TS16 overhead.

In E1 Receive Clock Slave mode, RSFSn inputs the pulse at a rate of integer multiple of 125 µs to indicate the start of

a frame.

RSFSn is updated/sampled on the active edge of the corresponding RSCKn. The active polarity of RSFSn is selected

by the FSINV bit (b4, T1/J1-048H,... / b4, E1-048H,...).

MRSFS: Multiplexed Receive Side System Frame Pulse for Link 1 ~ 2

In Receive Multiplexed mode, MRSFS inputs the pulse at a rate of integer multiple of 125 µs to indicate the start of a

frame on the multiplexed data bus. MRSFS is sampled on the active edge of MRSCK. The active polarity of MRSFS is

selected by the FSINV bit (b4, T1/J1-048H,... / b4, E1-048H,...).

RSFS[1:2]/MRSCK are Schmitt-triggered inputs/outputs with pull-up resistors.

RSCK[1] / MRSCK Output / Input 80 RSCK[1:2]: Receive Side System Clock for Link 1 ~ 2

RSCK[2]

72 In Receive Clock Master mode, the RSCKn pins output a (gapped) 1.544 MHz (for T1/J1 mode) / 2.048 MHz (for E1

mode) clock used to update the signal on the corresponding RSDn, RSIGn and RSFSn pins.

In Receive Clock Slave mode, the RSCKn pins input a 1.544 MHz (for T1/J1 mode only), 2.048 MHz or 4.096 MHz

clock used to update the signals on the corresponding RSDn and RSIGn pins and sample the signals on the corre-

sponding RSFSn pins. Selected by the RSLVCK bit (b4, T1/J1-010H / b4, E1-010H), the RSCK[1] pin can be used for

both two links.

MRSCK: Multiplexed Receive Side System Clock for Link 1 ~ 2

In Receive Multiplexed mode, MRSCK inputs a 8.192 MHz or 16.384 MHz clock used to update the signals on the

MRSD and MRSIG pins and sample the signal on the MRSFS pin.

TSD[1] / MTSD

Input

TSD[2]

RSCK[1:2]/MRSCK are Schmitt-triggered inputs/outputs with pull-up resistors.

75 TSD[1:2]: Transmit Side System Data for Link 1 ~ 2

67 The data stream from the system side is input on these pins.

In Transmit Clock Master mode, the TSDn pins are sampled on the active edge of the corresponding TSCKn.

In Transmit Clock Slave mode, selected by the TSLVCK bit (b1, T1/J1-010H / b1, E1-010H), the TSDn pins are sam-

pled on the active edge of the corresponding TSCKn or both two TSDn pins are sampled on the active edge of

TSCK[1].

MTSD: Multiplexed Transmit Side System Data for Link 1 ~ 2

In Transmit Multiplexed mode, the MTSD pin is used to input the data stream. Using a byte-interleaved multiplexing

scheme, the MTSD pin inputs the data for Link 1 and Link 2. The data on the MTSD pin is sampled on the active edge

of MTSCK.

TSD[1]/MTSD is a Schmitt-triggered input. TSD[2] is a Schmitt-triggered input with pull-up resistor.

Pin Description

16

August 20, 2009

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