IDT79R4640100DU Просмотр технического описания (PDF) - Integrated Device Technology

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IDT79R4640100DU

LOW-COST EMBEDDED ORION™ RISC MICROPROCESSOR

Integrated Device Technology 

R4640/RV4640

COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE

word data cycles or 8 single word cycles, and whether a

single data transfer larger than 4 bytes should be broken

into two smaller transfers.

Handshake Signals

There are six handshake signals on the system

interface. Two of these, RdRdy* and WrRdy* are used by

an external device to indicate to the R4640 whether it can

accept a new read or write transaction. The R4640

samples these signals before deasserting the address on

read and write requests.

ExtRqst* and Release* are used to transfer control of

the SysAD and SysCmd buses between the processor

and an external device. When an external device needs

to control the interface, it asserts ExtRqst*. The R4640

responds by asserting Release* to release the system

interface to slave state.

ValidOut* and ValidIn* are used by the R4640 and the

external device respectively to indicate that there is a

valid command or data on the SysAD and SysCmd

buses. The R4640 asserts ValidOut* when it is driving

these buses with a valid command or data, and the

external device drives ValidIn* when it has control of the

buses and is driving a valid command or data.

Non-overlapping System Interface

The R4640 requires a non-overlapping system

interface, compatible with the R4700. This means that

only one processor request may be outstanding at a time

and that the request must be serviced by an external

device before the R4640 issues another request. The

R4640 can issue read and write requests to an external

device, and an external device can issue read and write

requests to the R4640.

The R4640 asserts ValidOut* and simultaneously

drives the address and read command on the SysAD and

SysCmd buses. If the system interface has RdRdy* or

Read transactions asserted, then the processor tristates

its drivers and releases the system interface to slave state

by asserting Release*. The external device can then

begin sending the data to the R4640.

Figure 5 shows a processor block read request and the

external agent read response. The read latency is 4

cycles (ValidOut* to ValidIn*), and the response data

pattern is DDxxDD. Figure 6 shows a processor block

write.

Write Reissue and Pipeline Write

The R4700 and the R4640 implement additional write

protocols designed to improve performance. This imple-

mentation doubles the effective write bandwidth. The

write re-issue has a high repeat rate of 2 cycles per write.

A write issues if WrRdy is asserted 2 cycles earlier and is

still asserted at the issue cycle. If it is not still asserted,

the last write re-issues again. Pipelined writes have the

same 2-cycle per write repeat rate, but can issue one

more write after WrRdy* de-asserts. They still follow the

issue rule as R4x00 mode for other writes.

External Requests

The R4640 responds to requests issued by an external

device. The requests can take several forms. An external

device may need to supply data in response to an R4640

read request or it may need to gain control over the

system interface bus to access other resources which

may be on that bus.

The following is a list of the supported external

requests:

• Read Response

• Null

Boot-Time Options

Fundamental operational modes for the processor are

initialized by the boot-time mode control interface. The

boot-time mode control interface is a serial interface

operating at a very low frequency (MasterClock divided by

256). The low-frequency operation allows the initialization

information to be kept in a low-cost EPROM; alternatively

the twenty-or-so bits could be generated by the system

interface ASIC or a simple PAL.

Immediately after the VCCOK Signal is asserted, the

processor reads a serial bit stream of 256 bits to initialize

all fundamental operational modes. After initialization is

complete, the processor continues to drive the serial clock

output, but no further initialization bits are read.

Boot-Time Modes

The boot-time serial mode stream is defined in Table 5.

Bit 0 is the bit presented to the processor when VCCOK is

asserted; bit 255 is the last.

Power Management

CP0 is also used to control the power management for

the R4640. This is the standby mode and it can be used to

reduce the power consumption of the internal core of the

CPU. The standby mode is entered by executing the WAIT

instruction with the SysAD bus idle and is exited by any

interrupt.

Standby Mode Operation

The R4640 provides a means to reduce the amount of

power consumed by the internal core when the CPU

would otherwise not be performing any useful operations.

This is known as “Standby Mode”.

Entering Standby Mode

Executing the WAIT instruction enables interrupts and

enters Standby mode. When the WAIT instruction finishes

the W pipe-stage, if the SysAd bus is currently idle, the

internal clocks will shut down, thus freezing the pipeline.

The PLL, internal timer, and some of the input pins

(Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset*) will

continue to run. If the conditions are not correct when the

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