IDT79R4640100DU Просмотр технического описания (PDF) - Integrated Device Technology
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IDT79R4640100DU Datasheet PDF : 23 Pages
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R4640/RV4640
COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE
64 bits-per-cycle to minimize the cache miss penalty. The without changing cache contents.
line size is eight instructions (32 bytes) to maximize • Writeback. Loads and instruction fetches will first
performance.
search the cache, reading main memory only if the
In addition, the contents of one set of the instruction desired data is not cache resident. On data store opera-
cache (set “A”) can be “locked” by setting a bit in a CP0 tions, the cache is first searched to see if the target
register. Locking the set prevents its contents from being address is cache resident. If it is resident, the cache
overwritten by a subsequent cache miss; refill occurs then contents will be updated, and the cache line marked for
only into “set B”.
later writeback. If the cache lookup misses, the target
This operation effectively “locks” time critical code into line is first brought into the cache before the cache is
one 4kB set, while allowing the other set to service other updated.
instruction streams in a normal fashion. Thus, the benefits • Write-through with write allocate. Loads and instruc-
of cached performance are achieved, while deterministic tion fetches will first search the cache, reading main
real-time response is preserved.
memory only if the desired data is not cache resident.
Data Cache
For fast, single cycle data access, the R4640 includes
an 8KB on-chip data cache that is two-way set
associative with a fixed 32-byte (eight words) line size.
Table 4 lists the R4640 cache attributes.
On data store operations, the cache is first searched to
see if the target address is cache resident. If it is resi-
dent, the cache contents will be updated and main
memory will also be written; the state of the “writeback”
bit of the cache line will be unchanged. If the cache
lookup misses, the target line is first brought into the
Characteristics
Size
Instruction
8KB
Data
8KB
cache before the cache is updated.
• Write-through without write-allocate. Loads and
instruction fetches will first search the cache, reading
Organization
Line size
2-way set associa- 2-way set associa-
tive
tive
32B
32B
main memory only if the desired data is not cache resi-
dent. On data store operations, the cache is first
searched to see if the target address is cache resident.
Index
Tag
vAddr11..0
pAddr31..12
vAddr11..0
pAddr31..12
If it is resident, the cache contents will be updated, and
the cache line marked for later writeback. If the cache
lookup misses, then only main memory is written.
Write policy
Line transfer order
Miss restart after
transfer of
Parity
n.a.
read sub-block
order
write sequential
entire line
per-word
writeback /writethru Associated with the Data Cache is the store buffer.
read sub-block
order
write sequential
first word
When the R4640 executes a Store instruction, this single-
entry buffer gets written with the store data while the tag
comparison is performed. If the tag matches, then the
data is written into the Data Cache in the next cycle that
the Data Cache is not accessed (the next non-load cycle).
per-byte
The store buffer allows the R4640 to execute a store
every processor cycle and to perform back-to-back stores
Cache locking
set A
set A
without penalty.
Table 4: R4640 Cache Attributes
The data cache is protected with byte parity and its tag
is protected with a single parity bit. It is virtually indexed
and physically tagged to allow simultaneous address
translation and data cache access
The normal write policy is writeback, which means that
a store to a cache line does not immediately cause
memory to be updated. This increases system perfor-
mance by reducing bus traffic and eliminating the
bottleneck of waiting for each store operation to finish
before issuing a subsequent memory operation. Software
can however select write-through for certain address
ranges, using the CAlg register in CP0. Cache protocols
supported for the data cache are:
• Uncached. Addresses in a memory area indicated as
uncached will not be read from the cache. Stores to
such addresses will be written directly to main memory,
Write buffer
Writes to external memory, whether cache miss write-
backs or stores to uncached or write-through addresses,
use the on-chip write buffer. The write buffer holds up to
four address and data pairs. The entire buffer is used for
a data cache writeback and allows the processor to
proceed in parallel with memory update. For uncached
and write-through stores, the write buffer significantly
increases performance over the R4000 family of
processors.
System Interface
The R4640 supports a 64-bit system interface that is
bus compatible with the R4700 system interface. In
addition, the R4640 supports a 32-bit system interface
mode, allowing the CPU to interface directly with a lower
cost memory system.
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