IDT79R4640100DU Просмотр технического описания (PDF) - Integrated Device Technology

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IDT79R4640100DU

LOW-COST EMBEDDED ORION™ RISC MICROPROCESSOR

Integrated Device Technology 

R4640/RV4640

COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE

DESCRIPTION

The IDT79R4640 is a low-cost member of the

Integrated Device Technology, Inc. ORION family, targeted

to a variety of performance-hungry embedded applica-

tions. The R4640 continues the ORION tradition of high-

performance through high-speed pipelines, high-band-

width caches and bus interface, 64-bit architecture, and

careful attention to efficient control. The cost of this

performance is reduced by removing functional units

frequently not required for many embedded applications.

The R4640 supports a wide variety of embedded

processor-based applications, such as internetworking

equipment (routers, switches), office automation equip-

ment (printers, scanners), and consumer multimedia

game systems. Also, being upwardly software-compatible

with the RISController family as well as bus- and upwardly

software-compatible with the IDT ORION family, the R4640

will serve in many of the same applications. And, the

R4640 supports applications that require integer digital

signal processing (DSP) functions.

The R4640 brings ORION performance levels to lower

cost systems. ORION performance is preserved by

retaining large on-chip two-way set-associative caches, a

streamlined high-speed pipeline, high bandwidth, 64-bit

execution, and facilities such as early restart for data

cache misses.

These techniques allow the system designer over 1.8

GB/sec aggregate internal bandwidth, 266 MB/sec bus

bandwidth, almost 200 Dhrystone MIPS, 50MFlops, and

75 M Mul-Add/sec. An array of tools facilitates rapid

development of R4640-based systems, allowing a wide

variety of customers access to the processor’s high-

performance capabilities while maintaining short time-to-

market goals.

HARDWARE OVERVIEW

R4640 is software-compatible with the R4650, and

includes the instruction set found in the R4700 micropro-

cessor, targeted at higher performance while maintaining

binary compatibility with earlier R30xx processors. The

extensions result in better code density, greater multi-

processing support, improved performance for commonly

used code sequences in operating system kernels, and

faster execution of floating-point intensive applications. All

resource dependencies are made transparent to the

programmer, insuring transportability among implementa-

tions of the MIPS instruction set architecture. In addition,

MIPS-III specifies new instructions defined to take

advantage of the 64-bit architecture of the processor.

Finally, the R4640 also implements additional instruc-

tions, which are considered extensions to the MIPS-III

architecture. These instructions improve the multiply and

multiply-add throughput of the CPU, making it well suited

to a wide variety of imaging and DSP applications. These

extensions, which use opcodes allocated by MIPS

Technologies for this purpose, are supported by a wide

variety of development tools.

The MIPS integer unit implements a load/store archi-

tecture with single cycle ALU operations (logical, shift,

add, sub) and autonomous multiply/divide unit. The 64-bit

register resources include: 32 general-purpose

orthogonal integer registers, the HI/LO result registers for

the integer multiply/divide unit, and the program counter.

In addition, the on-chip floating-point co-processor adds

32 floating-point registers, and a floating-point

control/status register.

Register File

The R4640 has 32 general-purpose 64-bit registers.

These registers are used for scalar integer operations and

address calculation. The register file consists of two read

ports and one write port and is fully bypassed to minimize

operation latency in the pipeline.

Some key elements of the R4640 are briefly

described below. More detailed information is available in

the IDT79R4640/IDT79R4650 RISC Processor Hard-

ware User’s Manual.

Pipeline

The R4640 uses a 5-stage pipeline that is similar to

the IDT79R3000 and the IDT79R4700 processors. The

simplicity of this pipeline allows the R4640 to cost less

than super-scalar processors and require less power than

super-pipelined processors. So, unlike superscalar

processors, applications that have large data dependen-

cies or require a great deal of load/stores can still achieve

peak performance.

Arithmetic Logic Unit

The R4640 ALU consists of the integer adder and

logic unit. The adder performs address calculations in

addition to arithmetic operations; the logic unit performs

all of the logic and shift operations. Each unit is highly

optimized and can perform an operation in a single pipe-

line cycle.

Integer Multiply/Divide

The R4640 uses a dedicated integer multiply/divide

unit, optimized for high-speed multiply and multiply-

accumulate operation. Table 1 shows the performance,

expressed in terms of pipeline clocks, achieved by the

R4640 integer multiply unit.

Integer Execution Engine

The R4640 implements the MIPS-III Instruction Set

Architecture, and thus is fully upward compatible with

applications running on the earlier generation parts. The

2

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