ICS9248F-78 Просмотр технического описания (PDF) - Integrated Circuit Systems
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ICS9248F-78 Datasheet PDF : 13 Pages
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ICS9248 - 78
Preliminary Product Preview
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
Description
-
X
FS3#
-
X
FS0#
-
X
FS2#
27
1
24MHz (Act/Inact)
-
1
(Reserved)
26
1
48MHz (Act/Inact)
-
1
(Reserved)
30
1 SDRAM_F (Act/Inact)
Byte 2: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
Description
31
1 SDRAM7 (Act/Inact)
32
1 SDRAM6 (Act/Inact)
34
1 SDRAM5 (Act/Inact)
35
1 SDRAM4 (Act/Inact)
36
1 SDRAM3 (Act/Inact)
38
1 SDRAM2 (Act/Inact)
39
1 SDRAM1 (Act/Inact)
40
1 SDRAM0 (Act/Inact)
Byte 3: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
Description
20
1 PCICLK7 (Act/Inact)
19
1 PCICLK6 (Act/Inact)
17
1 PCICLK5 (Act/Inact)
16
1 PCICLK4 (Act/Inact)
15
1 PCICLK3 (Act/Inact)
13
1 PCICLK2 (Act/Inact)
12
1 PCICLK1 (Act/Inact)
11
1 PCICLK0 (Act/Inact)
Byte 4: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
Description
-
0
(Reserved)
7
1 3V66_0 (Act/Inact)
8
1 3V66_1 (Act/Inact)
-
X
SEL_3V66
46
1 IOAPIC (Act/Inact0)
-
X
FS1#
43
1 CPUCLK1 (Act/Inact)
44
1 CPUCLK0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured
at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
7
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