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EN6360QI

8A PowerSoC Highly Integrated Synchronous DC-DC Buck with Integrated Inductor

Altera Corporation 

EN6360QI

PARAMETER

POK Deglitch Delay

SYMBOL

TEST CONDITIONS

Falling Edge Deglitch Delay After

Output Crossing 90% level.

FSW=1.2 MHz

MIN TYP MAX UNITS

213

µs

VPOK Logic Low level

VPOK Logic high level

POK Internal pull-up

resistor

With 4mA Current Sink into POK Pin

0.4

V

VIN

V

94

kΩ

Current Balance

VOUT Rise Time

Accuracy

With 2 to 4 Converters in Parallel,

the Difference Between Nominal

∆IOUT

and Actual Current Levels.

∆VIN<50mV; RTRACE< 10 mΩ,

+/-10

%

Iload= # Converter * IMAX

∆TRISE

(Note 4)

tRISE [ms] = CSS [nF] x 0.065;

10nF ≤ CSS ≤ 30nF;

(Note 5 and Note 6)

-25

+25

%

ENABLE Logic High

ENABLE Logic Low

VENABLE_HIGH

VENABLE_LOW

2.5V ≤ VIN ≤ 6.6V;

1.2

VIN

V

0

0.8

V

ENABLE Pin Current

M/S Ternary Pin Logic

Low

IEN

VT-LOW

VIN = 6.6V

Tie M/S Pin to GND

50

µA

0

0.7

V

M/S Ternary Pin Logic

Float

VT-FLOAT

M/S Pin is Open

1.1

1.4

V

M/S Ternary Pin Logic

Hi (Note 7)

VT-HIGH

Pull Up to VIN through an external

resistor REXT . Refer to Figure 7.

1.8

V

Ternary Pin Input

Current

Binary Pin Logic Low

Threshold

ITERN

VB-LOW

2.5V ≤ VIN ≤ 4V, REXT = 15kΩ

4V < VIN ≤ 6.6V, REXT = 51kΩ

ENABLE, S_IN

117

88

µA

0.8

V

Binary Pin Logic High

Threshold

VB-HIGH

ENABLE, S_IN

1.8

V

S_OUT Low Level

S_OUT High Level

VS_OUT_LOW

VS_OUT_HIGH

0.4

V

2.0

V

Note 3: POK threshold when VOUT is rising is nominally 92%. This threshold is 90% when VOUT is falling. After crossing

the 90% level, there is a 256 clock cycle (~213µs at 1.2 MHz) delay before POK is de-asserted. The 90% and 92% levels

are nominal values. Expect these thresholds to vary by ±3%.

Note 4: Parameter not production tested but is guaranteed by design.

Note 5: Rise time calculation begins when AVIN > VUVLO and ENABLE = HIGH.

Note 6: VOUT Rise Time Accuracy does not include soft-start capacitor tolerance..

Note 7: M/S pin is ternary. Ternary pins have three logic levels: high, float, and low. This pin is meant to be strapped to

VIN through an external resistor, strapped to GND, or left floating. The state cannot be changed while the device is on.

06489

March 24, 2015

www.altera.com/enpirion, Page 6

Rev G

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