EN6360QI Просмотр технического описания (PDF) - Altera Corporation

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EN6360QI

8A PowerSoC Highly Integrated Synchronous DC-DC Buck with Integrated Inductor

Altera Corporation 

PIN

26-27,

62-63

28-34

35-43

46

47

48

49

50

51

52

53

54

55

56

57

58

60

61

69

EN6360QI

NAM E

NC(SW)

PGND

PVIN

VDDB

BGND

S_IN

S_OUT

POK

ENABLE

AVIN

AGND

M/S

VFB

EAOUT

SS

VSENSE

FQADJ

EN_PB

PGND

FUNCTION

NO CONNECT: These pins are internally connected to the common switching node of the

internal MOSFETs. They must be soldered to PCB but not be electrically connected to any

external signal, ground, or voltage. Failure to follow this guideline may result in device damage.

Input and output power ground. Connect these pins to the ground electrode of the input and

output filter capacitors. Refer to VOUT, PVIN descriptions and Layout Recommendation for

more details.

Input power supply. Connect to input power supply and place input filter capacitor(s) between

these pins and PGND pins 32 to 34.

Internal regulated voltage used for the internal control circuitry. Decouple with an optional

0.1µF capacitor to BGND for improved efficiency. This pin may be left floating if board space is

limited.

Ground for VDDB. Refer to pin 46 description.

Digital input. A high level on the M/S pin will make this EN6360QI a Slave and the S_IN will

accept the S_OUT signal from another EN6360QI for parallel operation. A low level on the M/S

pin will make this device a Master and the switching frequency will be phase locked to an

external clock. Leave this pin floating if it is not used.

Digital output. A low level on the M/S pin will make this EN6360QI a Master and the internal

switching PWM signal is output on this pin. This output signal is connected to the S_IN pin of

another EN6360QI device for parallel operation. Leave this pin floating if it is not used.

POK is a logic level high when VOUT is within -10% to +20% of the programmed output

voltage (0.9VOUT_NOM ≤ VOUT ≤ 1.2VOUT_NOM). This pin has an internal pull-up resistor to AVIN

with a nominal value of 94kΩ.

Device enable pin. A high level or floating this pin enables the device while a low level disables

the device. A voltage ramp from another power converter may be applied for precision enable.

Refer to Power Up Sequencing

Analog input voltage for the control circuits. Connect this pin to the input power supply (PVIN)

at a quiet point. Can also be connected to an auxiliary supply within a voltage range that is

sequencing.

The quiet ground for the control circuits. Connect to the ground plane with a via right next to the

pin.

Ternary (three states) input pin. Floating this pin disables parallel operation. A low level

configures the device as Master and a high level configures the device as a Slave. A REXT

resistor is recommended to pulling M/S high. Refer to Ternary Pin description in the Functional

Description section for REXT values. Also refer to S_IN and S_OUT pin descriptions.

This is the external feedback input pin. A resistor divider connects from the output to AGND.

The mid-point of the resistor divider is connected to VFB. A feed-forward capacitor (CA) and

resistor (R1) are required parallel to the upper feedback resistor (RA). The output voltage

regulation is based on the VFB node voltage equal to 0.600V. For Slave devices, leave VFB

floating.

Error amplifier output. Allows for customization of the control loop. May be left floating.

A soft-start capacitor is connected between this pin and AGND. The value of the capacitor

controls the soft-start interval. Refer to Soft-Start in the Functional Description for more details.

This pin senses output voltage when the device is in pre-bias (or back-feed) mode. Connect

VSENSE to VOUT when EN_PB is high or floating. Leave floating when EN_PB is low.

Frequency adjust pin. This pin must have a resistor to AGND which sets the free running

frequency of the internal oscillator.

Enable pre-bias input. When this pin is pulled high, the device will support monotonic start-up

under a pre-biased load. VSENSE must be tied to VOUT for EN_PB to function. This pin is

pulled high internally. Enable pre-bias feature is not available for parallel operations.

Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heat-

sinking purposes. Refer to Layout Recommendation section.

06489

March 24, 2015

www.altera.com/enpirion, Page 3

Rev G

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