EN5312QI Просмотр технического описания (PDF) - Altera Corporation

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EN5312QI

1A PowerSoC Synchronous Buck Regulator With Integrated Inductor

Altera Corporation 

LAYOUT CONSIDERATIONS*

EN5312QI

*Optimized PCB Layout file downloadable from the Altera website to assure first pass design success.

Recommendation 1: Input and output filter capacitors should be placed on the same side of the

PCB, and as close to the EN5312QI package as possible. They should be connected to the device

with very short and wide traces. Do not use thermal reliefs or spokes when connecting the capacitor

pads to the respective nodes. The +V and GND traces between the capacitors and the EN5312QI

should be as close to each other as possible so that the gap between the two nodes is minimized,

even under the capacitors.

Recommendation 2: DO NOT connect GND pins 3 and 4 together. Pin 3 should be used for the

Input capacitor local ground and pin 4 should be used for the output capacitor ground. The ground

pad for the input and output filter capacitors should be isolated ground islands and should be

connected to system ground as indicated in recommendation 3 and recommendation 5.

Recommendation 3: Multiple small vias (0.25mm after copper plating) should be used to connect

ground terminals of the Input capacitor and the output capacitor to the system ground plane. This

provides a low inductance path for the high-frequency AC currents; thereby reducing ripple and

suppressing EMI (see Fig. 6, Fig. 7, and Fig. 8).

Recommendation 4: The large thermal pad underneath the component must be connected to the

system ground plane through as many thermal vias as possible. The vias should use 0.33mm drill

size with minimum one ounce copper plating (0.035mm plating thickness). This provides the path for

heat dissipation from the converter.

Recommendation 5: The system ground plane referred to in recommendations 3 and 4 should be

the first layer immediately below the surface layer (PCB layer 2). This ground plane should be

continuous and un-interrupted below the converter and the input and output capacitors that carry

large AC currents. If it is not possible to make PCB layer 2 a continuous ground plane, an

uninterrupted ground “island” should be created on PCB layer 2 immediately underneath the

EN5312QI and its input and output capacitors. The vias that connect the input and output capacitor

grounds, and the thermal pad to the ground island, should continue through to the PCB GND layer as

well.

Recommendation 6: As with any switch-mode DC/DC converter, do not run sensitive signal or

control lines underneath the converter package.

Recommendation 7: The VOUT sense point should be just after the last output filter capacitor next

to the device. Keep the sense trace short in order to avoid noise coupling into the node.

Recommendation 8: Keep Ra, Ca, and Rb close to the VFB pin (see Figures 4 and 5). The VFB pin

is a high-impedance, sensitive node. Keep the trace to this pin as short as possible. Whenever

possible, connect Rb directly to the GND pin instead of going through the GND plane.

Figure 6 shows an example schematic for the EN5312QI using the internal voltage select. In this

example, the device is set to a VOUT of 1.5V (VS2=0, VS1=1, VS0=1).

Figure 7 shows an example schematic using an external voltage divider. VS0=VS1=VS2= “1”. The

resistor values are chosen to give an output voltage of 2.6V.

04535

11

December 14, 2015

www.altera.com/enpirion

Rev E

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