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DS2141AQ Просмотр технического описания (PDF) - Maxim Integrated

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Компоненты Описание
производитель
DS2141AQ
MaximIC
Maxim Integrated MaximIC
DS2141AQ Datasheet PDF : 39 Pages
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DS2141A
link. The device fully meets all of the latest T1 specifications including ANSI T1.403-1989, AT&T TR
62411 (12-90), and CCITT G.704 and G.706.
1.0 INTRODUCTION
The DS2141A T1 Controller has four main sections: the receive side, the transmit side, the line interface
controller, and the parallel control port. See the block diagram below. On the receive side, the device will
clock in the serial T1 stream via the RPOS and RNEG pins. The synchronizer will locate the frame and
multiframe patterns and establish their respective positions. This information will be used by the rest of
the receive side circuitry.
The DS2141A is an “off-line” framer, which means that all of the T1 serial stream that goes into the
device will come out of it unchanged. Once the T1 data has been framed to, the robbed-bit signaling data
and FDL can be extracted. The 2-frame elastic stores can either be enabled or bypassed.
The transmit side clocks in the unframed T1 stream at TSER and adds in the framing pattern, the robbed-
bit signaling, and the FDL. The line interface control port will update line interface devices that contain a
serial port. The parallel control port contains a multiplexed address and data structure which can be
connected to either a microcontroller or microprocessor.
DS2141A BLOCK DIAGRAM
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