DS2181A Просмотр технического описания (PDF) - Maxim Integrated

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производитель

DS2181A

CEPT Primary Rate Transceiver

Maxim Integrated 

DS2181A

NOTE:

1. When the common channel signaling mode is enabled (TCR.5 = 1), the TSD input is disabled

internally; all timeslot 16 data is sampled at TSER.

CCR: COMMON CONTROL REGISTER Figure 5

(MSB)

-

TAFP

THDE

RHDE

TCE

RCE

(LSB)

SAS

LLB

SYMBOL

-

TAFP

THDE

RHDE

TCE

RCE

SAS

LLB

POSITION

CCR.7

CCR.6

CCR.5

CCR.4

CCR.3

CCR.2

CCR.1

CCR.0

NAME AND DESCRIPTION

Reserved; must be 0 for proper operation.

Transmit Align Frame Position1

When clear, the CAS multiframe begins with a frame containing

the frame alignment signal. When set, the CAS multiframe begins

with a frame not containing the frame alignment signal.

Transmit HDB3 Enable

0 = Outgoing data at TPOS and TNEG is AMI coded.

1 = Outgoing data at TPOS and TNEG is HDB3 coded.

Receive HDB3 Enable

0 = Incoming data at RPOS and RNEG is AMI coded.

1 = Incoming data is RPOS and RNEG is HDB3 coded.

Transmit CRC4 Enable

When set, outgoing international bit positions in frames 0 through

12 and 14 are replaced by CRC4 multiframe alignment and

checksum words.

Receive CRC4 Enable

0 = Disable CRC4 multiframe synchronizer.

1 = Enable CRC4 synchronizer; search for CRC4 multiframe

alignment once frame alignment complete.

Sync Algorithm Select

0 = Use old DS2181 sync algorithm

1 = Use new DS2181A sync algorithm

Local Loopback

0 = Normal operation.

1 = Internally loop TPOS, TNEG, and TCLK to RPOS, RNEG,

and RCLK.

NOTES:

1. This bit must be cleared when CRC4 multiframe mode is enabled (CCR.3 = 1); its state does not

affect CCS framing (RCR.5 = 1).

2. CCR is considered a receive register and operates from RCLK and SCLK.

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