DS2181A Просмотр технического описания (PDF) - Maxim Integrated

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производитель

DS2181A

CEPT Primary Rate Transceiver

Maxim Integrated 

DS2181A

REGISTER SUMMARY Table 5

REGISTE ADDRE T/R1

R

SS

DESCRIPTION/FUNCTION

RIMR

RSR

0000

0001

R Receive Interrupt Mask Register. Allows masking of alarm

generated interrupts.

R2 Receive Status Register. Reports all receive alarm conditions.

BVCR

0010

R Bipolar Violation Count Register. 8-bit presettable counter

which records individual bipolar violations.

CECR

0011

R CRC4 Error Count Register. 8-bit presettable counter which

records individual errors.

FECR

0100

R Frame Error Count Register. 8-bit presettable counter which

logs individual errors in the received frame alignment signal.

RCR

0101

R Receive Control Register. Establishes receive side operating

characteristics.

CCR

0110

T/R Common Control Register. Establishes additional operating

characteristics for transmit and receive sides.

TCR

0111

T Transmit Control Register. Establishes transmit side operation

characteristics.

TIR1

TIR2

1000

1001

T Transmit Idle Registers. Designates which outgoing timeslots are

to be substituted with idle code.

TIR3

1010

TIR4

1011

TINR

1100

T Transmit International and National Register. When enabled via

the TCR, contents inserted into the outgoing national and/or

international bit positions.

TXR

1101

T Transmit Extra Register. When enabled via the TCR, contents

inserted into the out going extra bit positions.

NOTES:

1. Transmit or receive side register.

2. RSR is a read only register; all other registers are read/write.

3. Reserved bit locations must be programmed to 0.

SERIAL PORT INTERFACE

Pins 14 through 18 of the DS2181A serve as a microprocessor/ microcontroller-compatible serial port.

Fourteen on-chip registers allow the user to update operational characteristics and monitor device status

via a host controller, minimizing hardware interfaces.

Port read/write timing is unrelated to the chip transmit and receive timing, allowing asynchronous reads

and/ or writes by the host. The timing set is identical to that of 8051-type microcontrollers operating in

serial port mode 0. For proper operation of the port and the transmit and receive registers, the user should

provide TCLK and RCLK as well as SCLK.

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