BUK102-50GL Просмотр технического описания (PDF) - Philips Electronics
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производитель
BUK102-50GL Datasheet PDF : 11 Pages
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Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK102-50GL
Energy & Time
1.5
1.0
Energy / J
BUK102-50GL
Time / ms
0.5
Tj(TO)
0
-60
-20
20
60
100 140 180 220
Tmb / C
Fig.14. Typical overload protection characteristics.
Conditions: VDD = 13 V; VIS = 5 V; SC load = 30 mΩ
ID / A
50
BUK102-50GL
40
30
typ.
20
10
0
50
60
70
VDS / V
Fig.15. Typical clamping characteristics, 25 ˚C.
ID = f(VDS); conditions: VIS = 0 V; tp ≤ 50 µs
VIS(TO) / V
2
1
max.
typ.
min.
0
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
Fig.16. Input threshold voltage.
VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V
IIS / uA
500
BUK102-50GL
400
300
200
100
0
0
Fig.17.
2
4
6
8
VIS / V
Typical DC input characteristics, Tj = 25 ˚C.
IIS = f(VIS); normal operation
IIS / mA
5
4
3
PROTECTION LATCHED
RESET
BUK102-50GL
2
1
NORMAL
0
0
2
4
6
8
VIS / V
Fig.18. Typical DC input characteristics, Tj = 25 ˚C.
IISL = f(VIS); overload protection operated ⇒ ID = 0 A
IS / A
200
BUK102-50GL
150
100
50
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VSD / V
Fig.19. Typical reverse diode current, Tj = 25 ˚C.
IS = f(VSDS); conditions: VIS = 0 V; tp = 250 µs
January 1993
7
Rev 1.200
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