TINY1634-15MZ Просмотр технического описания (PDF) - Atmel Corporation
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TINY1634-15MZ Datasheet PDF : 259 Pages
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During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM and as a result the stack size is only limited by the total SRAM size and the
usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are
executed). The stack pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through
the five different addressing modes supported in the AVR® architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All interrupts have a separate interrupt vector in the interrupt vector table. The interrupts have priority in accordance
with their interrupt vector position. The lower the interrupt vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as control registers, SPI and other I/O functions.
The I/O memory can be accessed directly, or as the data space locations following those of the register file 0x20 - 0x5F. In
addition, the Atmel® ATtiny1634 has extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and
LD/LDS/LDD instructions can be used.
5.2 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a
single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are
executed. The ALU operations are divided into three main categories—arithmetic, logical, and bit functions. Some
implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and
fractional format. For more information, see the external “AVR Instruction Set” document and Section 28. “Instruction Set
Summary” on page 248.
5.3 Status Register
The status register contains information about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform conditional operations. Note that the status register is
updated after all ALU operations. In many cases this makes using the dedicated compare instructions unnecessary,
resulting in faster and more compact code. For more information, see the external “AVR Instruction Set” document and
Section 28. “Instruction Set Summary” on page 248.
The status register is neither automatically stored when entering an interrupt routine nor restored when returning from an
interrupt. This must be handled by software.
5.4 General Purpose Register File
The register file is optimized for the AVR-enhanced RISC instruction set. In order to achieve the required performance and
flexibility, the following input/output schemes are supported by the register file:
● One 8-bit output operand and one 8-bit result input
● Two 8-bit output operands and one 8-bit result input
● Two 8-bit output operands and one 16-bit result input
● One 16-bit output operand and one 16-bit result input
ATtiny1634 [PRELIMINARY DATASHEET]
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9296C–AVR–07/14
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