NCP1615 Просмотр технического описания (PDF) - ON Semiconductor
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NCP1615 Datasheet PDF : 46 Pages
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NCP1615
Table 5. ELECTRICAL CHARACTERISTICS (VCC = 15 V, VHV = 120 V, VFB = 2.4 V, RHVFB = 200 kW, VHVFB = 20 V, CVControl =
10 nF, VFFcontrol = 2.6 V, VZCD/CS = 0 V, RZCD/CS = 3 kW, VFOVPBUV = 2.4 V, VSTDBY = 1 V, VRestart = 1 V, VPSTimer = 0 V, VFault = open,
VPFCOK = open, CDRV = 1 nF, for typical values TJ = 25°C, for min/max values, TJ is −40°C to 125°C, unless otherwise noted)
Characteristics
Conditions
Symbol
Min
Typ
Max Unit
REGULATION BLOCK
Error Amplifier Current
Source
Sink
Open Loop Error Amplifier Transconduc-
tance
VFB = 2.4 V, VVControl = 2 V
VFB = 2.6 V, VVControl = 2 V
VFB = VREF +/− 100 mV
IEA(SRC)
IEA(SNK)
gm
16
20
24
mA
16
20
24
180
210
245
mS
Maximum Control Voltage
Minimum Control Voltage
EA Output Control Voltage Range
DRE Detect Threshold
DRE Threshold Hysteresis
Ratio between the DRE Detect Threshold
and the Regulation Level
VFB = 2 V
VControl(MAX)
–
4.5
–
V
VFB = 2.6 V
VControl(MIN)
–
0.5
–
V
VControl(MAX) − VControl(MIN)
DVControl
3.9
4.0
4.1
V
VFB decreasing
VDRE
–
2.388
–
V
VFB increasing
VDRE(HYS)
–
–
25
mV
VFB decreasing, VDRE / VREF
KDRE
95.0
95.5
96.0
%
Control Pin Source Current During Start−Up PFCOK = Low, VVControl = 2 V IControl(start−up) 80
(C/D Version)
100
113
mA
EA Boost Current During Start−Up
(C/D Version)
Iboost(start−up)
–
80
–
mA
Control Pin Source Current During DRE
EA Boost Current During DRE
PFC GATE DRIVE
VVControl = 2 V
IControl(DRE)
180
220
250
mA
Iboost(DRE)
–
200
–
mA
Rise Time (10−90%)
Fall Time (90−10%)
Source Current Capability
Sink Current Capability
High State Voltage
Low Stage Voltage
ZERO CURRENT DETECTION
VDRV from 10 to 90% of VDRV
tDRV(rise)
–
90 to 10% of VDRV
tDRV(fall)
–
VDRV = 0 V
IDRV(SRC)
−
VDRV = 12 V
IDRV(SNK)
−
VCC = VCC(off) + 0.2 V,
RDRV = 10 kW
VCC = 28 V, RDRV = 10 kW
VDRV(high1)
8
VDRV(high2)
10
VSTDBY = 0 V
VDRV(low)
–
40
80
ns
20
60
ns
500
−
mA
800
−
mA
–
–
V
12
14
–
0.25
V
Zero Current Detection Threshold
ZCD and Current Sense Ratio
Positive Clamp Voltage
CS/ZCD Input Bias Current
ZCD Propagation Delay
Minimum detectable ZCD Pulse Width
Maximum Off−Time (Watchdog Timer)
Missing Valley Timeout Timer
Pull−Up Current Source
Source Current for CS/ZCD Impedance
Testing
VCS/ZCD rising
VCS/ZCD falling
VZCD(rising)
675
750
825 mV
VZCD(falling)
200
250
300
VZCD(rising)/VILIM
KZCD/ILIM
1.4
1.5
1.6
–
ICS/ZCD = 0.75 mA
ICS/ZCD = 5 mA
VCS/ZCD(MAX1) 7.1
7.4
7.8
V
VCS/ZCD(MAX2) 15.4
15.8
16.1
VCS/ZCD = VZCD(rising)
VCS/ZCD = VZCD(falling)
ICS/ZCD(bias1)
0.5
–
2.0
mA
ICS/ZCD(bias2)
0.5
–
2.0
Measured from VCS/ZCD =
VZCD(falling) to DRV rising
tZCD
–
60
200
ns
Measured from VZCD(rising) to
VZCD(falling)
tSYNC
–
110
200
ns
VCS/ZCD > VZCD(rising)
toff1
80
200
320
ms
toff2
700 1000 1300
Measured after last ZCD transition
ttout
20
30
50
ms
Detects open pin fault.
ICS/ZCD1
–
1
–
mA
Pulls up at the end of toff1
ICS/ZCD2
–
250
–
mA
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