MC141519T Просмотр технического описания (PDF) - Motorola => Freescale

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MC141519T

LCD Segment Driver

Motorola => Freescale 

OPERATION OF LIQUID CRYSTAL DISPLAY DRIVER

INTRODUCTION

The LCD segment driver can support multiplex ratio of a

LCD system up to 80 and cascading of more than one driver

for expansion is possible. It can be set from 1:5 bias (for 16

mux) to 1:10 bias (for 80 mux), by the voltage divider ratio of

Fig.2. The ratio of bias or the contrast ratio (a) is defined as

1: 4----x----R---R-1----1-+-----R-----2- =1:a

As the multiplex ratio changes, the ratio of bias has to be

changed accordingly. The ratio of bias relates to the multiplex

ratio as

a= mux +1

To set up a multiplex ratio, please refer to

MC68HC05L11D/H Technical Data Section 10.

CONTROL LOGIC produces the control signals neces-

sary for display RAM read / write and serial data latching. This

Control Logic is directly supervised by the MCU through the

Data Bus, i.e. D0 - D6, CR1 and CR2. MCU writing a byte of

instruction to the Segment Control Register will cause Seg-

ment Driver(s) to fetch this instruction from the Data Bus and

the command executed at the next P02 cycle. Fig.1 shows the

functions of which the Control Logic will carry out in respond to

MCU access through the Segment Control Register.

ROW ADDRESS(WRITE IN) instruction causes Segment

driver(s) to load the content of the SHIFT REGISTER into a

row of RAM which address is specified by D6 to D0.

ROW ADDRESS(READ FROM) instruction causes Seg-

ment driver(s) to copy a row of RAM which address is specified

by D6 to D0 into the 160 BIT SHIFT REGISTER.

SCROLL UP ADVANCE instruction causes Segment driv-

er(s) to do a vertical scroll up or down.

The content of D6 to D0 only represents the vertical offset

of the new screen to the current screen. This vertical offset

presenting in the Data Bus then is added up with an old offset

which is stored in a register called the VERTICAL SCROLL

VECTOR REGISTER to generate a new offset. This new offset

will then be stored in the VERTICAL SCROLL VECTOR REG-

ISTER. Periodically the content of this register will be fetched

and loaded into a presettable counter in the TIMING LOGIC to

generate the row addresses for screen refreshing.

RESET BIT0 Writing a “1” to this bit will set the VERTICAL

SCROLL VECTOR REGISTER to zero.

UL

BIT1 If this bit is set, the segment driver serves

the upper panel in case of splitted panel.

This will cause a swap in signals flow

between SD1 and SD2.

CLRSH BIT2 Writing an “1” to this bit will clear the content

of the 160-BIT SHIFT REGISTER.

TIMING LOGIC, according to M, BPCLK and FRM, fills the

DISPLAY DATA LATCH ARRAY with rows of RAM matrix’s con-

tent periodically starting from the row address specified by the

VERTICAL SCROLL VECTOR REGISTER.

VOLTAGES SELECTOR consists of switching circuit to

select appropriate voltage levels from the external voltage

divider. (See Fig. 2).

DISPLAY DATA LATCH ARRAY is used to buffer up a row of

display data from RAM.

STATIC RAM MATRIX consists of 160x80 bits of SRAM cell.

The content of these RAM cells can be altered by read/write from/

to the shift register with the Segment Control Interface (refer to

MC68HC05L11D/H Technical Data Section 10).

HIGH VOLTAGE DRIVERS ARRAY is a row of high voltage

drivers connecting to segment lines of any LCD panel. The out-

put waveform of the high voltage driver is shown as Seg(x) in Fig

3.

SHIFT REGISTER is a 160-bit bi-directional register which

acts as an input either from SD1 or SD2. The direction of data flow

depends on the content of DDIR. And, it can be swapped by set-

ting the UL bit to high. Data enter this shift register in serial. Shift

register latches data at the falling edge of the signal SHCLK. See

Timing Diagram for illustration.

MOTOROLA

MC141519

3–101

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