VIPER50B Просмотр технического описания (PDF) - STMicroelectronics

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производитель

VIPER50B

SMPS PRIMARY I.C.

STMicroelectronics 

VIPER50B/BSP

Figure 22: Recommended layout

C1

Frominput

diodes bri dge

R1

2

VDD

-

1 OSC

13V

+

U1

VIPer50B

3

DRAIN

COMP SOURCE

5

4

R2

C2

C3

ISO1

C4

T1

D2

D1

C7 To secondary

filtering and load

C5

C6

FC00500

LAYOUT CONSIDERATIONS

Some simple rules insure a correct running of

switching power supplies. They may be classified

into two categories:

- To minimise power loops: the way the switched

power current must be carefully analysed and

the corresponding paths must present the

smallest inner loop area as possible. This

avoids radiated EMC noises, conducted EMC

noises by magnetic coupling, and provides a

better efficiency by eliminating parasitic

inductances, especially on secondary side.

- To use different tracks for low level signals and

power ones. The interferences due to a mixing

of signal and power may result in instabilities

and/or anomalous behaviour of the device in

case of violent power surge (Input

overvoltages, output short circuits...).

In case of VIPer, these rules apply as shown on

figure 22. The loops C1-T1-U1, C5-D2-T1,

C7-D1-T1 must be minimised. C6 must be as

close as possible from T1. The signal

components C2, ISO1, C3 and C4 are using a

dedicated track to be connected directly to the

source of the device.

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