Z80185_ Просмотр технического описания (PDF) - Zilog

Номер в каталоге

Компоненты Описание

производитель

Z80185_

Family MPU

Zilog 

Z8018x Family

MPU User Manual

x

Figure 21. SLEEP Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 22. I/O Address Relocation . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 23. Logical Address Mapping Examples . . . . . . . . . . . . . . . . . 55

Figure 24. Physical Address Transition . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 25. MMU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 26. I/O Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 27. Logical Memory Organization . . . . . . . . . . . . . . . . . . . . . 58

Figure 28. Logical Space Configuration . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 29. Physical Address Generation . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 30. Physical Address Generation 2 . . . . . . . . . . . . . . . . . . . . . 64

Figure 31. Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 32. TRAP Timing Diagram -2nd Op Code Undefined . . . . . . 71

Figure 33. TRAP Timing - 3rd Op Code Undefined . . . . . . . . . . . . . 72

Figure 34. NMI Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 35. NMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 36. INT0 Mode 0 Timing Diagram . . . . . . . . . . . . . . . . . . . . . 76

Figure 37. INT0 Mode 1 Interrupt Sequence . . . . . . . . . . . . . . . . . . . 77

Figure 38. INT0 Mode 1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 39. INT0 Mode 2 Vector Acquisition . . . . . . . . . . . . . . . . . . . 79

Figure 40. INT0 Interrupt Mode 2 Timing Diagram . . . . . . . . . . . . . 80

Figure 41. INT1, INT2 Vector Acquisition . . . . . . . . . . . . . . . . . . . . 81

Figure 42. RETI Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 43. INT1, INT2 and Internal Interrupts Timing Diagram . . . . 86

Figure 44. Refresh Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . 87

Figure 45. DMAC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 46. DMA Timing Diagram-CYCLE STEAL Mode . . . . . . . 106

Figure 47. CPU Operation and DMA Operation DREQ0

is Programmed for Level-Sense . . . . . . . . . . . . . . . . . . . 107

Figure 48. CPU Operation and DMA Operation DREQ0

is Programmed for Edge-Sense . . . . . . . . . . . . . . . . . . . . 108

UM005001-ZMP0400

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