Z80181_ Просмотр технического описания (PDF) - Zilog

Номер в каталоге

Компоненты Описание

производитель

Z80181_

Family MPU

Zilog 

Z8018x Family

MPU User Manual

ix

List of Figures

Z80180, Z8S180, Z8L180 MPU Operation . . . . . . . . . . . . . . . . . . . .1

Figure 1. 64-Pin DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Figure 2. 68-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Figure 3. 80-Pin QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Figure 4. Z80180/Z8S180/Z8L180 Block Diagram . . . . . . . . . . . . . . .6

Figure 5. Operation Mode Control Register . . . . . . . . . . . . . . . . . . . .15

Figure 6. M1 Temporary Enable Timing . . . . . . . . . . . . . . . . . . . . . .16

Figure 7. I/O Read and Write Cycles with IOC = 1

Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 8. I/O Read and Write cycles with IOC = 0

Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 9. Op Code Fetch (without Wait State) Timing Diagram . . . .19

Figure 10. Op Code Fetch (with Wait State) Timing Diagram . . . . . .20

Figure 11. Memory Read/Write (without Wait State)

Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 12. Memory Read/Write (with Wait State)

Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 13. I/O Read/Write Timing Diagram . . . . . . . . . . . . . . . . . . . .23

Figure 14. Instruction Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 15. RESET Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 16. Bus Exchange Timing During Memory Read . . . . . . . . . . .26

Figure 17. Bus Exchange Timing During CPU Internal Operation . . .27

Figure 18. WAIT Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 19. Memory and I/O Wait State Insertion

(DCNTL – DMA/Wait Control Register) . . . . . . . . . . . . . .29

Figure 20. HALT Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .33

UM005001-ZMP0400

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