Z80195_ Просмотр технического описания (PDF) - Zilog

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Z80195_

Family MPU

Zilog 

Z 8018x Fam ily

M PU Us e r M anual

19

The Op Code on the data bus is latched at the rising edge of T3 and the

bus cycle terminates at the end of T3.

Phi

A0–A19

D0–D7

T1

T2

T3

T1

T2

WAIT

M1

MREQ

RD

Figure 9. Op Code Fetch (without Wait State) Timing Diagram

Figure 10 illustrates the insertion of Wait States (TW) into the Op Code

fetch cycle. Wait States (TW) are controlled by the external WAIT input

combined with an on-chip programmable Wait State generator.

At the falling edge of T2 the combined WAIT input is sampled. If WAIT

input is asserted Low, a Wait State (TW) is inserted. The address bus,

MREQ, RD and M1 are held stable during Wait States. When WAIT is

sampled inactive High at the falling edge of TW, the bus cycle enters T3

and completes at the end of T3.

UM005001-ZMP0400

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