Z80195_ Просмотр технического описания (PDF) - Zilog

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Z80195_

Family MPU

Zilog 

Z 8018x Fam ily

M PU Us e r M anual

18

The user must program the Operation Mode Control Register

Note: before the first I/O instruction is executed.

CPU Timing

This section explains the Z8X180 CPU timing for the following operations:

• Instruction (Op Code) fetch timing

• Operand and data read/write timing

• I/O read/write timing

• Basic instruction (fetch and execute) timing

• RESET timing

• BUSREQ/BUSACK bus exchange timing

The basic CPU operation consists of one or more Machine Cycles (MC).

A machine cycle consists of three system clocks, T1, T2, and T3 while

accessing memory or I/O, or it consists of one system clock (T1) during

CPU internal operations. The system clock is half the frequency of the

Crystal oscillator (that is, an 8-MHz crystal produces 4 MHz or 250 nsec).

For interfacing to slow memory or peripherals, optional Wait States (TW)

may be inserted between T2 and T3.

Instruction (Op Code) Fetch Timing

Figure 9 illustrates the instruction (Op Code) fetch timing with no Wait

States. An Op Code fetch cycle is externally indicated when the M1

output pin is Low.

In the first half of T1, the address bus (A0 –A19) is driven from the

contents of the Program Counter (PC). This address bus is the translated

address output of the Z8X180 on-chip MMU.

In the second half of T1, the MREQ. (Memory Request) and RD (Read)

signals are asserted Low, enabling the memory.

UM005001-ZMP0400

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