Z80182_ Просмотр технического описания (PDF) - Zilog

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Z80182_

Family MPU

Zilog 

Z 8018x Fam ily

M PU Us e r M anual

14

Central Processing Unit

The CPU is microcoded to provide a core that is object code compatible

with the Z80 CPU. It also provides a superset of the Z80 instruction set,

including 8-bit multiply and divide. This core has been enhanced to allow

many of the instructions to execute in fewer clock cycles.

DMA Controller

The DMA controller provides high speed transfers between memory and

I/O devices. Transfer operations supported are memory-to-memory,

memory to/from I/O and I/O to I/O. Transfer modes supported are

REQUEST, BURST, and CYCLE STEAL. DMA transfers can access the

full 1MB addressing range with a block length up to 64KB, and can cross

over 64K boundaries.

Asynchronous Serial Communications Interface (ASCI)

The ASCI logic provides two individual full-duplex UARTs. Each

channel includes a programmable baud rate generator and modem control

signals. The ASCI channels can also support a multiprocessor

communications format.

Programmable Reload Timer (PRT)

This logic consists of two separate channels, each containing a 16-bit

counter (timer) and count reload register. The time base for the counters is

derived from the system clock (divided by 20) before reaching the

counter. PRT channel 1 provides an optional output to allow for

waveform generation.

Clocked Serial I/O (CSIO)

The CSIO channel provides a half-duplex serial transmitter and receiver.

This channel can be used for simple high-speed data connection to

another microprocessor or microcomputer.

UM005001-ZMP0400

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