Z80182_ Просмотр технического описания (PDF) - Zilog

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производитель

Z80182_

Family MPU

Zilog 

Z 8018x Fam ily

M PU Us e r M anual

11

TOUT. Timer Out (Output, Active High). TOUT is the pulse output from

PRT channel 1. This line is multiplexed with A18 of the address bus.

TXA0, TXA1. Transmit Data 0 and 1 (Outputs, Active High). These

signals are the transmitted data from the ASCI channels. Transmitted data

changes are with respect to the falling edge of the transmit clock.

TXS. Clocked Serial Transmit Data (Output, Active High). This line is

the transmitted data from the CSIO channel.

WAIT. Wait (Input; Active Low). WAIT indicates to the CPU that the

addressed memory or I/O devices are not ready for a data transfer. This

input is used to induce additional clock cycles into the current machine

cycle. The WAIT input is sampled on the falling edge of T2 (and

subsequent Wait States). If the input is sampled Low, then additional

Wait States are inserted until the WAIT input is sampled High, at which

time execution continues.

WR. Write (Output, Active Low, 3-state). WR indicates that the CPU data

bus holds valid data to be stored at the addressed I/O or memory location.

XTAL. Crystal (Input, Active High). Crystal oscillator connection. This

pin must be left open if an external clock is used instead of a crystal. The

oscillator input is not a TTL level (reference DC characteristics).

Multiplexed pins are described in Table 2.

UM005001-ZMP0400

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