Z80185_ Просмотр технического описания (PDF) - Zilog

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Z80185_

Family MPU

Zilog 

Z 8018x Fam ily

M PU Us e r M anual

13

• Programmable Reload Timers (PRT, 2 channels)

• Clock Serial I/O (CSIO) channel.

Other Z8X180 family members (such as Z80183, Z80S183, Z80185/195)

feature, in addition to these blocks, additional peripherals and are covered

in their associated Product Specification

Clock Generator

This logic generates the system clock from either an external crystal or

clock input. The external clock is divided by two and provided to both

internal and external devices.

Bus State Controller

This logic performs all of the status and bus control activity associated

with both the CPU and some on-chip peripherals. This includes Wait

State timing, RESET cycles, DRAM refresh, and DMA bus exchanges.

Interrupt Controller

This block monitors and prioritizes the variety of internal and external

interrupts and traps to provide the correct responses from the CPU. To

remain compatible with the Z80 CPU, three different interrupt modes are

supported.

Memory Management Unit

The MMU allows the user to map the memory used by the CPU (logically

only 64K) into the 1MB addressing range supported by the Z8X180. The

organization of the MMU object code features compatibility with the Z80

CPU while offering access to an extended memory space. This capability

is accomplished by using an effective common area - banked area

scheme.

UM005001-ZMP0400

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