Z80185_ Просмотр технического описания (PDF) - Zilog

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Z80185_

Family MPU

Zilog 

Z 8018x Fam ily

M PU Us e r M anual

16

T1

T2

T3

T1

T2

T3

Phi

WR

M1

Write into OMCR

Op Code Fetch

Figure 6. M1 Temporary Enable Timing

M1TE (M1 Temporary Enable): This bit controls the temporary assertion

of the M1 signal. It is always read back as a 1 and is set to 1 during

RESET. This function is used to arm the internal interrupt structure of the

Z80PIO. When a control word is written to the Z80PIO to enable

interrupts, no enable actually takes place until the PIO sees an active M1

signal. When M1TE is 1, there is no change in the operation of the M1

signal and M1E controls its function. When M1TE is 0, the M1 output is

asserted during the next Op Code fetch cycle regardless of the state

programmed into the M1E bit. This situation is only momentary (one

time) and the user need not reprogram a 1 to disable the function (See

Figure 7).

IOC: This bit controls the timing of the IORQ and RD signals. IOC is set

to 1 by RESET.

When IOC is 1, the IORQ and RD signals function the same as the

HD64180.

UM005001-ZMP0400

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