PE9721-01 Просмотр технического описания (PDF) - Peregrine Semiconductor Corp.

Номер в каталоге

Компоненты Описание

производитель

PE9721-01

2.7 GHz Integer-N PLL with Field-Programmable EEPROM

Peregrine Semiconductor Corp. 

PE9721

Preliminary Specification

Table 6. AC Characteristics

VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified

Symbol

Parameter

Control Interface and Registers (see Figure 3)

fClk

Serial data clock frequency

tClkH

Serial clock HIGH time

tClkL

Serial clock LOW time

tDSU

Data set-up time to Clock rising edge

tDHLD

Data hold time after Clock rising edge

tPW

S_WR pulse width

tCWR

Clock rising edge to S_WR rising edge

tCE

Clock falling edge to E_WR transition

tWRC

S_WR falling edge to Clock rising edge

tEC

E_WR transition to Clock rising edge

EEPROM Erase/Write Programming (see Figures 4 & 5)

tEESU

tEEPW

EELoad rising edge to VPP rising edge

VPP pulse width

Main Divider (Including Prescaler)

FIn

Operating frequency

PFIn

Input level range

Main Divider (Prescaler Bypassed)

FIn

Operating frequency

PFIn

Input level range

Reference Divider

fr

Operating frequency

Pfr

Reference input power (Note 4)

Phase Detector

fc

Comparison frequency

Conditions

Min

(Note 1)

30

30

10

10

30

30

30

30

30

500

50

500

External AC coupling

-5

(Note 2)

50

External AC coupling (Note 2)

-5

(Note 3)

Single ended input

-2

(Note 3)

Max

10

60

2700

5

270

5

100

20

Units

MHz

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ms

MHz

dBm

MHz

dBm

MHz

dBm

MHz

Note 1: fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fClk

specification.

Note 2:

CMOS logic levels can be used to drive FIn input if DC coupled and used in Prescaler Bypass mode. Voltage input needs to be a minimum of

0.5 Vp-p. For optimum phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns. No minimum frequency

limit exists when operated in this mode.

Note 3: Parameter is guaranteed through characterization only and is not tested.

Note 4: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum phase

noise performance, the reference input falling edge rate should be faster than 80 mV/ns.

PEREGRINE SEMICONDUCTOR CORP.  | http://www.peregrine-semi.com

Copyright  Peregrine Semiconductor Corp. 2003

Page 5 of 13

Share Link: