MWCT1111CLH Просмотр технического описания (PDF) - NXP Semiconductors.

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MWCT1111CLH

MWCT1xxx Reference Manual

NXP Semiconductors. 

Section number

Title

Page

12.2.14 Fast Interrupt 0 Match Register (INTC_FIM0)............................................................................................. 222

12.2.15 Fast Interrupt 0 Vector Address Low Register (INTC_FIVAL0)..................................................................222

12.2.16 Fast Interrupt 0 Vector Address High Register (INTC_FIVAH0)................................................................ 223

12.2.17 Fast Interrupt 1 Match Register (INTC_FIM1)............................................................................................. 223

12.2.18 Fast Interrupt 1 Vector Address Low Register (INTC_FIVAL1)..................................................................224

12.2.19 Fast Interrupt 1 Vector Address High Register (INTC_FIVAH1)................................................................ 224

12.2.20 IRQ Pending Register 0 (INTC_IRQP0)....................................................................................................... 224

12.2.21 IRQ Pending Register 1 (INTC_IRQP1)....................................................................................................... 225

12.2.22 IRQ Pending Register 2 (INTC_IRQP2)....................................................................................................... 225

12.2.23 IRQ Pending Register 3 (INTC_IRQP3)....................................................................................................... 226

12.2.24 IRQ Pending Register 4 (INTC_IRQP4)....................................................................................................... 226

12.2.25 IRQ Pending Register 5 (INTC_IRQP5)....................................................................................................... 227

12.2.26 IRQ Pending Register 6 (INTC_IRQP6)....................................................................................................... 227

12.2.27 Control Register (INTC_CTRL).................................................................................................................... 228

12.3 Functional Description..................................................................................................................................................229

12.3.1 Normal Interrupt Handling.............................................................................................................................229

12.3.2 Interrupt Nesting............................................................................................................................................ 229

12.3.3 Fast Interrupt Handling.................................................................................................................................. 230

12.4 Interrupts....................................................................................................................................................................... 230

Chapter 13

DMA Controller

13.1 Introduction...................................................................................................................................................................231

13.1.1 Overview........................................................................................................................................................ 231

13.1.2 Features.......................................................................................................................................................... 233

13.2 DMA Transfer Overview..............................................................................................................................................233

13.3 Memory Map/Register Definition.................................................................................................................................235

13.3.1 DMA Request Control Register (DMA_REQC)........................................................................................... 236

13.3.2 Source Address Register (DMA_SARn)....................................................................................................... 240

13.3.3 Destination Address Register (DMA_DARn)............................................................................................... 240

MWCT1xxx Reference Manual, Rev. 3.1, 09/2016

NXP Semiconductors

11

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