MPC8309VMAHFCA Просмотр технического описания (PDF) - Freescale Semiconductor

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MPC8309VMAHFCA

PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications

Freescale Semiconductor 

DDR2 SDRAM

The following figure shows the DDR SDRAM output timing for the MCK to MDQS skew measurement

(tDDKHMH).

MCK

MCK

tMCK

tDDKHMH(max) = 0.6 ns

MDQS

tDDKHMH(min) = –0.6 ns

MDQS

Figure 5. Timing diagram for tDDKHMH

The following figure shows the DDR2 SDRAM output timing diagram.

MCK[n]

MCK[n]

ADDR/CMD

MDQS[n]

MDQ[x]/

MECC[x]

tMCK

tDDKHAS ,tDDKHCS

tDDKHAX ,tDDKHCX

Write A0

NOOP

tDDKHMP

tDDKHMH

D0

tDDKHDX

tDDKHDS

tDDKLDS

D1

tDDKLDX

Figure 6. DDR2 SDRAM output timing diagram

tDDKHME

MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3

18

Freescale Semiconductor

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