MPC8309VMAHFCA Просмотр технического описания (PDF) - Freescale Semiconductor

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MPC8309VMAHFCA

PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications

Freescale Semiconductor 

DDR2 SDRAM

Table 12. DDR2 SDRAM DC electrical characteristics for GVDD(typ) = 1.8 V

Parameter/Condition

Symbol

Min

Max

Unit

Note

I/O supply voltage

GVDD

1.7

1.9

V

1

I/O reference voltage

MVREF

0.49 × GVDD

0.51 × GVDD

V

2

I/O termination voltage

VTT

MVREF – 0.04

MVREF + 0.04

V

3

Input high voltage

VIH

MVREF+ 0.125

GVDD + 0.3

V

—

Input low voltage

VIL

–0.3

MVREF – 0.125

V

—

Output leakage current

IOZ

–9.9

9.9

μA

4

Output high current (VOUT = 1.35 V)

IOH

–13.4

—

mA

—

Output low current (VOUT = 0.280 V)

IOL

13.4

—

mA

—

Notes:

1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.

2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak

noise on MVREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF. This rail should track variations in the DC level of MVREF.

4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.

Table 13. DDR2 SDRAM capacitance for GVDD(typ) = 1.8 V

Parameter/Condition

Symbol

Min

Max

Input/output capacitance: DQ, DQS

CIO

6

8

Delta input/output capacitance: DQ, DQS

CDIO

—

0.5

Note:

1. This parameter is sampled. GVDD = 1.8 V ± 0.100 V, f = 1 MHz, TA = 25 °C, VOUT = GVDD ÷ 2,

VOUT (peak-to-peak) = 0.2 V.

Unit

Note

pF

1

pF

1

6.2 DDR2 SDRAM AC electrical characteristics

This section provides the AC electrical characteristics for the DDR2 SDRAM interface.

6.2.1 DDR2 SDRAM input AC timing specifications

This table provides the input AC timing specifications for the DDR2 SDRAM (GVDD(typ) = 1.8 V).

Table 14. DDR2 SDRAM input AC timing specifications for 1.8-V interface

At recommended operating conditions with GVDD of 1.8 V± 100mV.

Parameter

Symbol

Min

Max

Unit

Note

AC input low voltage

AC input high voltage

VIL

—

MVREF – 0.25

V

—

VIH

MVREF + 0.25

—

V

—

The following table provides the input AC timing specifications for the DDR2 SDRAM interface.

MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor

15

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