HCPL-530K Просмотр технического описания (PDF) - Broadcom Corporation
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HCPL-530K
Broadcom Corporation
HCPL-530K Datasheet PDF : 16 Pages
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HCPL-5300, HCPL-5301, HCPL-530K, 5962-96852
Data Sheet
Switching Specifications (RL= 20 kΩ External)
Switching Specifications (RL= 20 kΩ External)
Over recommended operating conditions (TA = –55°C to +125°C, VCC = +4.5V to 30V, IF(ON) = 10 mA to 20 mA, VF(OFF) = –5V to 0.8V)
unless otherwise specified.
Parameter
Group A
Symbol Subgroupsa
Min
Typb
Max
Unit
Test Conditions
Fig Note
Propagation Delay Time
tPHL
to Low Output Level
Propagation Delay Time
tPLH
to High Output Level
Pulse Width Distortion
PWD
Propagation Delay
tPLH -tPHL
Difference Between Any
Two Parts
Output High Level
Common Mode
Immunity Transient
|CMH|
Output Low Level
Common Mode Transient
Immunity
|CML|
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9
9
30 180 450
— 100 —
250 350 650
— 130 —
— 150 450
–170 140 500
ns
CL = 100 pF IF(on) = 10 mA, 5, 7, c, d, e, f, g
ns
CL = 10 pF
VF(off) = 0.8V,
VCC = 15.0V,
9,-12
ns
CL = 100 pF VTHLH = 2.0V,
ns
CL = 10 pF
VTHHL = 1.5V
ns
CL = 100 pF
h
ns
i
10
17
—
kV/µs
IF = 0 mA,
VCC = 15.0V, 6, 17, j, k
VO > 3.0V
CL = 100 pF, 18, 21
VCM = 1000 VP-P
10
17
—
kV/µs IF = 10 mA
TA = 25°C
l, k
VO < 1.0V
a. Commercial parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD, Class H and K parts receive 100% testing at 25°C, +125°C, and –55°C (Subgroups 1
and 9, 2 and 10, 3 and 11 respectively).
b. All typical values at 25°C, VCC = 15V.
c. Pulse: f = 20 kHz, Duty Cycle = 10%.
d. The internal 20 kΩ resistor can be used by shorting pins 6 and 7 together.
e. Due to the tolerance of the internal resistor, and since propagation delay is dependent on the load resistor value, performance can be improved by using an
external 20 kΩ 1% load resistor. For more information on how propagation delay varies with load resistance, see Figure 8.
f. The RL = 20 kΩ, CL = 100 pF represents a typical IPM (Intelligent Power Module) load.
g. Use of a 0.1-μF bypass capacitor connected between pins 5 and 8 can improve performance by filtering power supply line noise.
h. Pulse Width Distortion (PWD) is defined as the difference between tPLH and tPHL for any given device.
i. The difference in tPLH and tPHL between any two parts under the same test condition. (See IPM Dead Time and Propagation Delay Specifications.)
j. Common mode transient immunity in a Logic High level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output
remains in a Logic High state (i.e., VO > 3.0V).
k. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to limits specified for all lots
not specifically tested.
l. Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output remains
in a Logic Low state (i.e., VO < 1.0V).
Broadcom
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