DSP56F826PB Просмотр технического описания (PDF) - Motorola => Freescale

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DSP56F826PB

16-bit Hybrid Controller

Motorola => Freescale 

Freescale Semiconductor, Inc.

Table 3. 56F826 Signal and Package Information for the 100 Pin LQFP

Signal

Name

Pin No.

Type

Description

PS

DS

RD

WR

TA0

(GPIOF0)

TA1

(GPIOF1)

TA2

(GPIOF2)

TA3

(GPIOF3)

TCK

TMS

TDI

TDO

29

Output

Program Memory Select—PS is asserted low for external program

memory access.

28

Output

Data Memory Select—DS is asserted low for external data memory

access.

26

Output

Read Enable—RD is asserted during external memory read cycles.

When RD is asserted low, pins D0–D15 become inputs and an external

device is enabled onto the device data bus. When RD is deasserted high,

the external data is latched inside the device. When RD is asserted, it

qualifies the A0–A15, PS, and DS pins. RD can be connected directly to

the OE pin of a Static RAM or ROM.

27

Output

Write Enable—WR is asserted during external memory write cycles.

When WR is asserted low, pins D0–D15 become outputs and the device

puts data on the bus. When WR is deasserted high, the external data is

latched inside the external device. When WR is asserted, it qualifies the

A0–A15, PS, and DS pins. WR can be connected directly to the WE pin of

a Static RAM.

91

Input/Output TA0–3—Timer A Channels 0, 1, 2, and 3

Input/Output Port F GPIO—These four General Purpose I/O (GPIO) pins can be

90

individually programmed as input or output.

After reset, the default state is Quad Timer.

89

88

100

Input

Test Clock Input—This input pin provides a gated clock to synchronize

(Schmitt) the test logic and shift serial data to the JTAG/OnCE port. The pin is

connected internally to a pull-down resistor.

1

Input

Test Mode Select Input—This input pin is used to sequence the JTAG

(Schmitt) TAP controller’s state machine. It is sampled on the rising edge of TCK

and has an on-chip pull-up resistor.

2

Input

Test Data Input—This input pin provides a serial input data stream to the

(Schmitt) JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-

chip pull-up resistor.

3

Output

Test Data Output—This tri-statable output pin provides a serial output

data stream from the JTAG/OnCE port. It is driven in the Shift-IR and

Shift-DR controller states, and changes on the falling edge of TCK.

10

56F826 Technical Data

For More Information On This Product,

Go to: www.freescale.com

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