30833FJGP Просмотр технического описания (PDF) - Renesas Electronics
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Компоненты Описание
производитель
30833FJGP Datasheet PDF : 527 Pages
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6.2 Setting Processor Mode .......................................................................................... 48
6.2.1 Applying VSS to CNVSS Pin ............................................................................ 48
6.2.2 Applying VCC to CNVSS Pin ............................................................................ 48
7. Bus................................................................................... 52
7.1 Bus Settings ............................................................................................................. 52
7.1.1 Selecting External Address Bus ...................................................................... 53
7.1.2 Selecting External Data Bus ............................................................................ 53
7.1.3 Selecting Separate/Multiplexed Bus ............................................................... 53
7.2 Bus Control ............................................................................................................... 55
7.2.1 Address Bus and Data Bus .............................................................................. 55
7.2.2 Chip-Select Signal ............................................................................................ 55
7.2.3 Read and Write Signals ..................................................................................... 57
7.2.4 Bus Timing ......................................................................................................... 58
7.2.5 ALE Signal ......................................................................................................... 62
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7.2.6 RDY Signal ......................................................................................................... 62
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7.2.7 HOLD Signal ...................................................................................................... 63
7.2.8 External Bus State when Accessing Internal Space...................................... 64
7.2.9 BCLK Output ..................................................................................................... 64
_______ __________ __________
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7.2.10 DRAM Control Signals (RAS, CASL, CASH and DW) .................................. 64
8. Clock Generation Circuit _______________________ 65
8.1 Types of Clock Generation Circuits........................................................................ 65
8.1.1 Main Clock ......................................................................................................... 74
8.1.2 Sub Clock .......................................................................................................... 75
8.1.3 On-chip Oscillator Clock .................................................................................. 76
8.1.4 PLL Clock .......................................................................................................... 77
8.2 CPU Clock and BCLK .............................................................................................. 79
8.3 Peripheral Function Clock ....................................................................................... 79
8.3.1 f1, f8, f32 and f2n ......................................................................................................................... 79
8.3.2 fAD .................................................................................................................................................... 79
8.3.3 fC32 .................................................................................................................................................. 80
8.4 Clock Output Function ............................................................................................ 80
8.5 Power Consumption Control .................................................................................. 80
8.5.1 Normal Operation Mode ................................................................................... 81
8.5.2 Wait Mode .......................................................................................................... 82
8.5.3 Stop Mode .......................................................................................................... 84
9. Protection ___________________________________ 88
A-2
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