30835FJGP Просмотр технического описания (PDF) - Renesas Electronics
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30835FJGP Datasheet PDF : 527 Pages
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22.1.13 CAN0 Error Interrupt Mask Register (C0EIMKR Register) ...................... 341
22.1.14 CAN0 Error Interrupt Status Register (C0EISTR Register) ..................... 342
22.1.15 CAN0 Global Mask Register, CAN0 Local Mask Register A and CAN0 Local Mask
Register B (C0GMRj (j=0 to4), C0LMARj and C0LMBRj Registers) .......... 343
22.1.16 CAN0 Message Slot i Control Register (C0MCTLi Register) (i=0 to 15) ... 346
22.1.17 CAN0 Slot Buffer Select Register (C0SBS Register) ............................... 349
22.1.18 Message Slot Buffer ................................................................................... 349
22.1.19 CAN0 Acceptance Filter Support Register (C0AFS Register)................. 354
22.2.2 CAN Transmit Timing ................................................................................... 355
22.2 Timing with CAN-Associated Registers ............................................................. 355
22.2.1 CAN Module Reset Timing ........................................................................... 355
22.2.3 CAN Receive Timing ..................................................................................... 356
22.2.4 CAN Bus Error Timing .................................................................................. 357
22.3 CAN Interrupts ...................................................................................................... 357
23. DRAMC ___________________________________ 359
23.1 DRAMC Multiplexed Address Output ................................................................. 361
23.2 Refresh .................................................................................................................. 361
23.2.1 Refresh ........................................................................................................... 361
23.2.2 Self-Refresh ................................................................................................... 361
24. Programmable I/O Ports _____________________ 366
24.1 Port Pi Direction Register (PDi Register, i=0 to 15)........................................... 366
24.2 Port Pi Register (Pi Register, i=0 to 15) .............................................................. 366
24.3 Function Select Register Aj (PSj Register) (j=0 to 3, 5 to 9) ............................. 366
24.4 Function Select Register Bk (PSLk Register) (k=0 to 3) ................................... 366
24.5 Function Select Register C (PSC Register) ....................................................... 367
24.6 Pull-up Control Register 0 to 4 (PUR0 to PUR4 Registers) .............................. 367
24.7 Port Control Register (PCR Register) ................................................................ 367
24.8 Input Function Select Register (IPS Register) ................................................... 367
24.9 Analog Input and Other Peripheral Function Input ........................................... 367
25. Flash Memory Version _______________________ 390
25.1 Memory Map ......................................................................................................... 391
25.1.1 Boot Mode ..................................................................................................... 392
25.2 Functions to Prevent the Flash Memory from Rewriting ................................. 392
25.2.1 ROM Code Protect Function ........................................................................ 392
25.2.2 ID Code Verify Function ............................................................................... 392
A-7
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