LTC1665 Просмотр технического описания (PDF) - Linear Technology

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LTC1665

Micropower Octal 8-Bit and 10-Bit DACs

Linear Technology 

TIMING DIAGRAM

t1

t2

SCK

t9

DIN

A3

t5

t7

CS/LD

DOUT

A3

t3

t4

A2

A1

t8

A2

A1

Figure 1

LTC1665/LTC1660

t6

t11

X1

X0

X1

X0

A3

166560 F01

OPERATION

Transfer Function

The transfer function is:

VO U T(ID E A L )

=

⎛

⎝⎜

k⎞

256 ⎠⎟

VREF

for

the

LTC1665

VO U T(ID E A L )

=

⎛

⎝⎜

k⎞

1024 ⎠⎟

VREF

for

the

LTC1660

where k is the decimal equivalent of the binary DAC input

code and VREF is the voltage at REF (Pin 6).

Power-On Reset

The LTC1665 clears the outputs to zero scale when power

is first applied, making system initialization consistent

and repeatable.

Power Supply Sequencing

The voltage at REF (Pin 6) should be kept within the range

– 0.2V ≤ VREF ≤ VCC + 0.2V (see Absolute Maximum Rat-

ings). Particular care should be taken to observe these

limits during power supply turn-on and turn-off sequences,

when the voltage at VCC (Pin 16) is in transition.

Serial Interface

Referring to Figure 2a (2b): With CS/LD held low, data

on the DIN input is shifted into the 16-bit shift register on

the positive edge of SCK. The 4-bit DAC address, A3-A0,

is loaded first (see Table 2), then the 8-bit (10-bit) input

code, D7-D0 (D9-D0), ordered MSB-to-LSB in each case.

Four (two) don’t-care bits, X3-X0 (X1-X0), are loaded last.

When the full 16-bit input word has been shifted in, CS/LD

is pulled high, loading the DAC register with the word

and causing the addressed DAC output(s) to update. The

clock is disabled internally when CS/LD is high. Note: SCK

must be low before CS/LD is pulled low.

The buffered serial output of the shift register is available

on the DOUT pin, which swings from GND to VCC. Data

appears on DOUT 16 positive SCK edges after being ap-

plied to DIN.

Multiple LTC1665/LTC1660’s can be controlled from a

single 3-wire serial port (i.e., SCK, DIN and CS/LD) by

using the included “daisy-chain” facility. A series of m

chips is configured by connecting each DOUT (except the

last) to DIN of the next chip, forming a single 16m-bit

shift register. The SCK and CS/LD signals are common

to all chips in the chain. In use, CS/LD is held low while m

16-bit words are clocked to DIN of the first chip; CS/LD

is then pulled high, updating all of them simultaneously.

166560fa

9

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