CY8C27643(2006) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY8C27643 Datasheet PDF : 51 Pages
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CY8C27x43 Final Data Sheet
1. Pin Information
1.1.2 20-Pin Part Pinout
Table 1-2. 20-Pin Part Pinout (SSOP, SOIC)
Pin
Type
Pin
No. Digital Analog Name
Description
1
IO
I
P0[7] Analog column mux input.
2
IO
IO P0[5] Analog column mux input and column output.
3
IO
IO P0[3] Analog column mux input and column output.
4
IO
I
P0[1] Analog column mux input.
5
Power
SMP Switch Mode Pump (SMP) connection to
external components required.
6
IO
P1[7] I2C Serial Clock (SCL).
7
IO
P1[5] I2C Serial Data (SDA).
8
IO
P1[3]
9
IO
P1[1]
Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*.
10
Power
Vss
Ground connection.
11
IO
P1[0]
Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*.
12
IO
P1[2]
13
IO
P1[4] Optional External Clock Input (EXTCLK).
14
IO
P1[6]
15
Input
XRES Active high external reset with internal pull
down.
16
IO
I
P0[0] Analog column mux input.
17
IO
IO P0[2] Analog column mux input and column output.
18
IO
IO P0[4] Analog column mux input and column output.
19
IO
I
P0[6] Analog column mux input.
20
Power
Vdd
Supply voltage.
CY8C27243 20-Pin PSoC Device
A, I,P0[7] 1
A,IO, P0[5] 2
A,IO, P0[3] 3
A,I, P0[1] 4
SMP 5
I2CSCL,P1[7] 6
I2CSDA,P1[5] 7
P1[3] 8
I2CSCL,XTALin,P1[1] 9
Vss 10
20
19
18
17
SSOP 16
SOIC 15
14
13
12
11
Vdd
P0[6], A,I
P0[4], A,IO
P0[2], A,IO
P0[0], A,I
XRES
P1[6]
P1[4],EXTCLK
P1[2]
P1[0],XTALout,I2CSDA
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
October 26, 2006
Document No. 38-12012 Rev. *K
9
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