EVAL-AD7782EB Просмотр технического описания (PDF) - Analog Devices
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EVAL-AD7782EB Datasheet PDF : 12 Pages
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AD7782
TIMING CHARACTERISTICS1, 2 (VDD = 2.7 V to 3.6 V or VDD = 4.75 V to 5.25 V; GND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V,
Logic 1 = VDD unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
(B Version)
Unit
Conditions/Comments
t1
tADC
t2
t3
t4
t53
t85
t9
t10
Slave Mode Timing
t6
t7
Master Mode Timing
t6
t7
t11
30.5176
50.54
0
0
60
80
2 × t ADC
0
60
80
10
80
0
10
80
100
100
t1/2
t1/2
t1/2
3t1/2
µs typ
ms typ
ns min
ns min
ns max
ns max
ns typ
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns max
ns min
ns min
µs typ
µs typ
µs min
µs max
Crystal Oscillator Period
19.79 Hz Update Rate
CH1/CH2 Select to CS Setup Time
CS Falling Edge to DOUT Active
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
Channel Settling Time
SCLK Active Edge to Data Valid Delay4
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
Bus Relinquish Time after CS Inactive Edge
CS Rising Edge to SCLK Inactive Edge Hold Time
SCLK Inactive to DOUT High
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK High Pulsewidth
SCLK Low Pulsewidth
DOUT Low to First SCLK Active Edge4
NOTES
1Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2See Figure 2.
3These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits.
4SCLK active edge is falling edge of SCLK.
5These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part
and as such are independent of external bus loading capacitances.
TO OUTPUT
PIN
50pF
ISINK (1.6mA WITH VDD = 5V
100A WITH VDD = 3V)
1.6V
ISOURCE( 200A WITH VDD = 5V
100A WITH VDD = 3V)
Figure 1. Load Circuit for Timing Characterization
–4–
REV. 0
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