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ADN4697E_

LVDS and M-LVDS Circuit Implementation Guide

Analog Devices 

Application Note

AN-1177

DIFFERENTIAL SIGNALLING AND LVDS/M-LVDS

Differential transmission is communication where two

VCC

VCC

complementary signals are transmitted, with the received signal

comprising the difference between the two signal lines. This

ADN4663

DOUT1+

RIN1+

ADN4664

form of communication, used by both LVDS and M-LVDS,

DIN1

100Ω

ROUT1

has two distinct advantages, high noise immunity and low

emissions.

DOUT1–

DOUT2+

RIN1–

RIN2+

The high noise immunity arises because typically a noise

DIN2

source couples equally onto both signal lines, leaving the

DOUT2–

100Ω

RIN2–

ROUT2

differential signal unaffected. Emissions from differential

signaling are low due to the tight coupling between the two

GND

GND

Figure 9. ADN4663 and ADN4664 2-Channel LVDS Point-to-Point

complementary signal lines when using a typical medium

(twisted pair cable, or closely placed strip line).

The distinction between LVDS and M-LVDS and other

differential signaling standards is that they have a low output

DEFINITIONS AND OUTPUT LEVELS

For LVDS and M-LVDS, one signal line is noninverting (that is,

high for a Logic 1 and low for a Logic 0) and the other signal

line is inverting (that is, the complement of the noninverting

signal). The difference in voltage between the two signal lines

is termed the differential voltage, VOD. VOD is also shorthand for

the magnitude of the differential voltage (positive or negative),

or |VOD|. The two signal lines each have a maximum voltage

swing of |VOD|, centered on the common-mode voltage, VOC

(also referred to as the offset voltage, VOS). The differential

voltage swings around 0 V. Typical LVDS signal levels are

swing. The differential output voltage and common mode range

specifications of LVDS and M-LVDS are shown in Figure 10. For

LVDS, the output voltage swing, |VOD|, is a minimum of 250 mV

and a maximum of 450 mV with a load of 100 Ω. This allows

low power operation and ensures that while transitions are fast,

to allow high data rates, the reduced output swing means that

the slew rate is not too severe. Rise and fall times are generally

in the region of hundreds of picoseconds, resulting in slew rates

of around 0.5 V/ns to 2.5 V/ns.

M-LVDS

4V

M-LVDS

LVDS

shown in Figure 8, together with the differential signal VOD

3V

LVDS

and common-mode voltage VOC. In this figure, VOUT+ is the

noninverting signal and VOUT− is the inverting signal.

LOGIC 1

LOGIC 0

LOGIC 1

2V

0V TO –1V TO

1V

2.4V

3.4V

250mV 450mV

480mV 650mV

VOUT+

VOUT–

1.35V

VOC = 1.2V

1.05V

|VOD|

0V

MIN

MAX

–1V

VOD

VOD

MIN

VOD

MAX

VOD

Figure 10. LVDS and M-LVDS Signaling Levels

VOD

(VOUT+ – VOUT–)

0.3V

0V

|VOD|

–0.3V

Figure 8. LVDS Output Levels

The differential voltage on an LVDS or M-LVDS bus is

generated by a driver current source. Noninverting LVDS driver

outputs or receiver inputs are generally denoted with a + and

inverting driver outputs or receiver inputs with a −.

Pin names are shown for the ADN4663 2-channel LVDS driver

and ADN4664 2-channel LVDS receiver in Figure 9. M-LVDS

follows the convention of RS-485 physical layer transceivers in

naming the bus lines A for the noninverting signal and B for the

inverting signal, or Y and Z for driver outputs on a full-duplex

transceiver.

M-LVDS has slew-rate limited drivers to enhance the robustness

of the signaling when there are additional impedance

discontinuities from multiple drivers/receivers and stubs. This

means that M-LVDS is limited to lower data rates compared to

LVDS. The ADN4690E through ADN4697E are available with

options for 100 Mbps or higher speed 200 Mbps. Another

characteristic of M-LVDS is increased driver strength, resulting

in a minimum output voltage swing |VOD| of 480 mV and a

maximum of 650 mV with a load of 50 Ω (two termination

resistors of 100 Ω, one either end of the bus).

RECEIVER THRESHOLDS

The receiver thresholds are the differential voltage levels above

or below which the received signal is considered a Logic 1 or a

Logic 0. For LVDS, a positive VOD >= +100 mV corresponds to

a Logic 1 and a negative VOD <= -100 mV corresponds to a

Logic 0.

Rev. 0 | Page 5 of 12

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