ADN2807ACP Просмотр технического описания (PDF) - Analog Devices
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ADN2807ACP Datasheet PDF : 20 Pages
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ADN2807
THEORY OF OPERATION
The ADN2807 is a delay-locked and phase-locked loop circuit
for clock recovery and data retiming from an NRZ encoded
data stream. The phase of the input data signal is tracked by two
separate feedback loops that share a common control voltage. A
high speed delay-locked loop path uses a voltage controlled
phase shifter to track the high frequency components of the
input jitter. A separate phase control loop, comprised of the
VCO, tracks the low frequency components of the input jitter.
The initial frequency of the VCO is set by a third loop, which
compares the VCO frequency with the reference frequency and
sets the coarse tuning voltage. The jitter tracking phase-locked
loop controls the VCO by the fine tuning control. The delay-
and phase-locked loops together track the phase of the input
data signal. For example, when the clock lags input data, the
phase detector drives the VCO to a higher frequency and also
increases the delay through the phase shifter. Both of these
actions serve to reduce the phase error between the clock and
data. The faster clock picks up phase while the delayed data
loses phase. Since the loop filter is an integrator, the static phase
error will be driven to zero.
Another view of the circuit is that the phase shifter implements
the zero required for the frequency compensation of a second-
order phase-locked loop. This zero is placed in the feedback
path and, therefore, does not appear in the closed-loop transfer
function. Jitter peaking in a conventional second-order phase-
locked loop is caused by the presence of this zero in the closed-
loop transfer function. Since this circuit has no zero in the
closed-loop transfer, jitter peaking is minimized.
The delay- and phase-locked loops together simultaneously
provide wideband jitter accommodation and narrow-band jitter
filtering. The linearized block diagram in Figure 13 shows that
the jitter transfer function, Z(s)/X(s), is a second-order low-pass
providing excellent filtering. Note that the jitter transfer has no
zero, unlike an ordinary second-order phase-locked loop. This
means the main PLL loop has low jitter peaking (Figure 14),
which makes this circuit ideal for signal regenerator
applications where jitter peaking in a cascade of regenerators
can contribute to hazardous jitter accumulation.
psh
INPUT X(s)
DATA
e(s)
d/sc
o/s
1/n
Z(s)
RECOVERED
CLOCK
d = PHASE DETECTOR GAIN
o = VCO GAIN
c = LOOP INTEGRATOR
psh = PHASE SHIFTER GAIN
n = DIVIDE RATIO
JITTER TRANSFER FUNCTION
Z(s) =
1
X(s)
s2
cn
do
n psh
+s o
+1
TRACKING ERROR TRANSFER FUNCTION
e(s)
=
s2
X(s)
s2 + s d
psh
c
+
do
cn
Figure 13. PLL/DLL Architecture
The error transfer, e(s)/X(s), has the same high-pass form as an
ordinary phase-locked loop. This transfer function is free to be
optimized to give excellent wideband jitter accommodation
since the jitter transfer function, Z(s)/X(s), provides the narrow-
band jitter filtering. See Table 4 for error transfer bandwidths
and jitter transfer bandwidths at the various data rates. The
delay-locked and phase-locked loops contribute to overall jitter
accommodation. At low frequencies of input jitter on the data
signal, the integrator in the loop filter provides high gain to
track large jitter amplitudes with small phase error. In this case,
the VCO is frequency modulated, and jitter is tracked as in an
ordinary phase-locked loop. The amount of low frequency jitter
that can be tracked is a function of the VCO tuning range. A
wider tuning range gives larger accommodation of low
frequency jitter. The internal loop control voltage remains small
for small phase errors, so the phase shifter remains close to the
center of its range and thus contributes little to the low
frequency jitter accommodation.
Rev. A | Page 10 of 20
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