AM29F004BT-90JI Просмотр технического описания (PDF) - Spansion Inc.
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AM29F004BT-90JI Datasheet PDF : 37 Pages
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DATA SHEET
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the internal
command register. The command register itself does not
occupy any addressable memory location. The register is
composed of latches that store the commands, along with the
address and data information needed to execute the com-
mand. The contents of the register serve as inputs to the
internal state machine. The state machine outputs dictate the
function of the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe each of
these operations in further detail.
Operation
Read
Write
CMOS Standby
TTL Standby
Output Disable
Temporary Sector Unprotect (See Note)
Table 1. Am29F004B Device Bus Operations
CE#
L
L
VCC ± 0.5 V
H
L
X
OE#
L
H
X
X
H
X
WE#
H
L
X
X
H
X
A0–A18
AIN
AIN
X
X
X
X
DQ0–DQ7
DOUT
DIN
High-Z
High-Z
High-Z
X
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: See the sections on Sector Protection and Temporary Sector
Unprotect for more information.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the CE# and OE# pins to VIL. CE# is the power control and
selects the device. OE# is the output control and gates array
data to the output pins. WE# should remain at VIH.
The internal state machine is set for reading array data upon
device power-up. This ensures that no spurious alteration of
the memory content occurs during the power transition. No
command is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data
on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
See Reading Array Data on page 13 for more information.
Refer to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for the
timing waveforms. ICC1 in the DC Characteristics table repre-
sents the active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive WE# and CE# to VIL, and
OE# to VIH.
An erase operation can erase one sector, multiple sectors, or
the entire device. The Sector Address Tables indicate the
address space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select a
sector. See the Command Definitions on page 13 section for
details on erasing a sector or the entire chip, or sus-
pending/resuming the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on DQ7–DQ0. Standard
read cycle timings apply in this mode. Refer to the Autoselect
Mode on page 10 and Autoselect Command Sequence sec-
tions for more information.
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The AC
Characteristics on page 24 section contains timing specifica-
tion tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may check
the status of the operation by reading the status bits on DQ7–
DQ0. Standard read cycle timings and ICC read specifications
apply. Refer to Write Operation Status on page 17 for more
information, and to each AC Characteristics section for timing
diagrams.
Standby Mode
When the system is not reading or writing to the device, it can
place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed
in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when CE# pin is
held at VCC ± 0.5 V. (Note that this is a more restricted voltage
range than VIH.) The device enters the TTL standby mode
when CE# pin is held at VIH. The device requires standard
access time (tCE) for read access when the device is in either
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
In the DC Characteristics tables, ICC3 represents the standby
current specification.
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Am29F004B
Am29F004B_00_E4 May 9, 2006
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