PCA9511ADR2G Просмотр технического описания (PDF) - ON Semiconductor

Номер в каталоге

Компоненты Описание

производитель

PCA9511ADR2G

Hot Swappable I2C-Bus and SMBus Bus Buffer

ON Semiconductor 

PCA9511A

capacitance between the two sides. The tPLH may be

negative if the output capacitance is less than the input

capacitance and would be positive if the output capacitance

is larger than the input capacitance, when the currents are the

same.

The tPHL can never be negative because the output does

not start to fall until the input is below 0.7 VCC, and the

output turn on has a non−zero delay, and the output has a

limited maximum slew rate, and even if the input slew rate

is slow enough that the output catches up, it will still lag the

falling voltage of the input by the offset voltage. The

maximum tPHL occurs when the input is driven LOW with

zero delay and the output is still limited by its turn−on delay

and the falling edge slew rate. The output falling edge slew

rate is a function of the internal maximum slew rate which

is a function of temperature, VCC and process, as well as the

load current and the load capacitance.

Rise Time Accelerators

During positive bus transitions, a 2 mA current source is

switched on to quickly slew the SDA and SCL lines HIGH

once the input level of 0.6 V for the PCA9511A is exceeded.

The rising edge rate should be at least 1.25 V/ms to guarantee

turn on of the accelerators. The built−in DV/Dt rise time

accelerators on all SDA and SCL lines require the bus

pull−up voltage and supply voltage (VCC) to be the same.

READY Digital Output

This pin provides a digital flag which is LOW when either

ENABLE is LOW, or the start−up sequence described

earlier in this section has not been completed. READY goes

HIGH when ENABLE is HIGH and start−up is complete.

The pin is driven by an open−drain pull−down capable of

sinking 3 mA while holding 0.4 V on the pin. Connect a

resistor of 10 kW to VCC to provide the pull−up.

ENABLE Low Current Disable

Grounding the ENABLE pin disconnects the backplane

side from the card side, disables the rise time accelerators,

drives READY LOW, disables the bus precharge circuitry,

and puts the part in a low current state. When the pin voltage

is driven all the way to VCC, the part waits for data

transactions on both the backplane and card sides to be

complete before reconnecting the two sides.

Resistor Pull−Up Value Selection

The system pull−up resistors must be strong enough to

provide a positive slew rate of 1.25 V/ms on the SDA and

SCL pins, in order to activate the boost pull−up currents

during rising edges. Choose maximum resistor value using

the formula given below:

ǒ Ǔ RPU v 800

103 VCC(min) * 0.6

C

where RPU is the pull−up resistor value in W, VCC(min) is the

minimum VCC voltage in volts, and C is the equivalent bus

capacitance in picofarads (pF).

In addition, regardless of the bus capacitance, always choose

RPU ≤ 65.7 kW for VCC = 5.5 V maximum, RPU ≤ 45 kW for

VCC = 3.6 V maximum. The start−up circuitry requires logic

HIGH voltages on SDAOUT and SCLOUT to connect the

backplane to the card, and these pull−up values are needed

to overcome the precharge voltage. See the curves in

Figures 4 and 5 for guidance in resistor pull−up selection.

http://onsemi.com

5

Share Link: